^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_X86_MPSPEC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_X86_MPSPEC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/mpspec_def.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/x86_init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/apicdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extern int pic_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Summit or generic (i.e. installer) kernels need lots of bus entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #if CONFIG_BASE_SMALL == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) # define MAX_MP_BUSSES 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define MAX_MP_BUSSES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_IRQ_SOURCES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern unsigned int def_to_bigsmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else /* CONFIG_X86_64: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_MP_BUSSES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif /* CONFIG_X86_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern int mp_bus_id_to_type[MAX_MP_BUSSES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern unsigned int boot_cpu_physical_apicid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern u8 boot_cpu_apic_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern unsigned long mp_lapic_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_X86_LOCAL_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern int smp_found_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define smp_found_config 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void get_smp_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) x86_init.mpparse.get_smp_config(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void early_get_smp_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) x86_init.mpparse.get_smp_config(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void find_smp_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) x86_init.mpparse.find_smp_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef CONFIG_X86_MPPARSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern void e820__memblock_alloc_reserved_mpc_new(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern int enable_update_mptable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern void default_find_smp_config(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern void default_get_smp_config(unsigned int early);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void e820__memblock_alloc_reserved_mpc_new(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define enable_update_mptable 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define default_find_smp_config x86_init_noop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define default_get_smp_config x86_init_uint_noop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int generic_processor_info(int apicid, int version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct physid_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long mask[PHYSID_ARRAY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) typedef struct physid_mask physid_mask_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define physid_set(physid, map) set_bit(physid, (map).mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define physid_clear(physid, map) clear_bit(physid, (map).mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define physid_isset(physid, map) test_bit(physid, (map).mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define physid_test_and_set(physid, map) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) test_and_set_bit(physid, (map).mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define physids_and(dst, src1, src2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define physids_or(dst, src1, src2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define physids_clear(map) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bitmap_zero((map).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define physids_complement(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define physids_empty(map) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bitmap_empty((map).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define physids_equal(map1, map2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define physids_weight(map) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bitmap_weight((map).mask, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define physids_shift_right(d, s, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define physids_shift_left(d, s, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline unsigned long physids_coerce(physid_mask_t *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return map->mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void physids_promote(unsigned long physids, physid_mask_t *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) physids_clear(*map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) map->mask[0] = physids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) physids_clear(*map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) physid_set(physid, *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) extern physid_mask_t phys_cpu_present_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* _ASM_X86_MPSPEC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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