Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _ASM_X86_MCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _ASM_X86_MCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <uapi/asm/mce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Machine Check support for x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* MCG_CAP register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MCG_CTL_P		BIT_ULL(8)   /* MCG_CTL register available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MCG_EXT_P		BIT_ULL(9)   /* Extended registers available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MCG_CMCI_P		BIT_ULL(10)  /* CMCI supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MCG_EXT_CNT_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MCG_SER_P		BIT_ULL(24)  /* MCA recovery/new status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MCG_ELOG_P		BIT_ULL(26)  /* Extended error log supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MCG_LMCE_P		BIT_ULL(27)  /* Local machine check supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* MCG_STATUS register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MCG_STATUS_RIPV		BIT_ULL(0)   /* restart ip valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MCG_STATUS_EIPV		BIT_ULL(1)   /* ip points to correct instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MCG_STATUS_MCIP		BIT_ULL(2)   /* machine check in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MCG_STATUS_LMCES	BIT_ULL(3)   /* LMCE signaled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* MCG_EXT_CTL register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCG_EXT_CTL_LMCE_EN	BIT_ULL(0) /* Enable LMCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* MCi_STATUS register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCI_STATUS_VAL		BIT_ULL(63)  /* valid error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MCI_STATUS_OVER		BIT_ULL(62)  /* previous errors lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCI_STATUS_UC		BIT_ULL(61)  /* uncorrected error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MCI_STATUS_EN		BIT_ULL(60)  /* error enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MCI_STATUS_MISCV	BIT_ULL(59)  /* misc error reg. valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MCI_STATUS_ADDRV	BIT_ULL(58)  /* addr reg. valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MCI_STATUS_PCC		BIT_ULL(57)  /* processor context corrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MCI_STATUS_S		BIT_ULL(56)  /* Signaled machine check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MCI_STATUS_AR		BIT_ULL(55)  /* Action required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MCI_STATUS_CEC_SHIFT	38           /* Corrected Error Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MCI_STATUS_CEC_MASK	GENMASK_ULL(52,38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MCI_STATUS_CEC(c)	(((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* AMD-specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MCI_STATUS_TCC		BIT_ULL(55)  /* Task context corrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MCI_STATUS_SYNDV	BIT_ULL(53)  /* synd reg. valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MCI_STATUS_DEFERRED	BIT_ULL(44)  /* uncorrected error, deferred exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCI_STATUS_POISON	BIT_ULL(43)  /* access poisonous data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCI_STATUS_SCRUB	BIT_ULL(40)  /* Error detected during scrub operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * McaX field if set indicates a given bank supports MCA extensions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *  - Deferred error interrupt type is specifiable by bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *    But should not be used to determine MSR numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *  - TCC bit is present in MCx_STATUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MCI_CONFIG_MCAX		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MCI_IPID_MCATYPE	0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MCI_IPID_HWID		0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * errors to indicate that errors are being filtered by hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * We should mask out bit 12 when looking for specific signatures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * of uncorrected errors - so the F bit is deliberately skipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * in this #define.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MCACOD		  0xefff     /* MCA Error Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MCACOD_DATA	0x0134	/* Data Load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MCACOD_INSTR	0x0150	/* Instruction Fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* MCi_MISC register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define  MCI_MISC_ADDR_PHYS	2	/* physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define  MCI_MISC_ADDR_MEM	3	/* memory address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define  MCI_MISC_ADDR_GENERIC	7	/* generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* CTL2 register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MCI_CTL2_CMCI_EN		BIT_ULL(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MCJ_CTX_MASK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MCJ_CTX_RANDOM		0    /* inject context: random */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MCJ_CTX_PROCESS		0x1  /* inject context: process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCJ_EXCEPTION		0x8  /* raise as exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCE_LOG_MIN_LEN 32U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCE_LOG_SIGNATURE	"MACHINECHECK"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* AMD Scalable MCA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSR_AMD64_SMCA_MC0_CTL		0xc0002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MSR_AMD64_SMCA_MC0_IPID		0xc0002005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSR_AMD64_SMCA_MC0_SYND		0xc0002006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define XEC(x, mask)			(((x) >> 16) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* mce.kflags flag bits for logging etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define	MCE_HANDLED_CEC		BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	MCE_HANDLED_UC		BIT_ULL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	MCE_HANDLED_EXTLOG	BIT_ULL(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define	MCE_HANDLED_NFIT	BIT_ULL(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	MCE_HANDLED_EDAC	BIT_ULL(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define	MCE_HANDLED_MCELOG	BIT_ULL(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * Indicates an MCE which has happened in kernel space but from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * which the kernel can recover simply by executing fixup_exception()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * so that an error is returned to the caller of the function that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * hit the machine check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCE_IN_KERNEL_RECOV	BIT_ULL(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * Indicates an MCE that happened in kernel space while copying data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * from user. In this case fixup_exception() gets the kernel to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * error exit for the copy function. Machine check handler can then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * treat it like a fault taken in user mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCE_IN_KERNEL_COPYIN	BIT_ULL(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * This structure contains all data related to the MCE log.  Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * carries a signature to make it easier to find from external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * debugging tools.  Each entry is only valid when its finished flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mce_log_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	char signature[12]; /* "MACHINECHECK" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned len;	    /* = elements in .mce_entry[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned recordlen;	/* length of struct mce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct mce entry[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Highest last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum mce_notifier_prios {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	MCE_PRIO_LOWEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	MCE_PRIO_MCELOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	MCE_PRIO_EDAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	MCE_PRIO_NFIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	MCE_PRIO_EXTLOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	MCE_PRIO_UC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	MCE_PRIO_EARLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	MCE_PRIO_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	MCE_PRIO_HIGHEST = MCE_PRIO_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct notifier_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) extern void mce_register_decode_chain(struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) extern void mce_unregister_decode_chain(struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) extern int mce_p5_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_ARCH_HAS_COPY_MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) extern void enable_copy_mc_fragile(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void enable_copy_mc_fragile(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #ifdef CONFIG_X86_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int mcheck_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void mcheck_cpu_init(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void mcheck_cpu_clear(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void mcheck_vendor_init_severity(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline int mcheck_init(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline void mcheck_vendor_init_severity(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifdef CONFIG_X86_ANCIENT_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void winchip_mcheck_init(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline void enable_p5_mce(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void mce_setup(struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void mce_log(struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DECLARE_PER_CPU(struct device *, mce_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Maximum number of MCA banks per CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MAX_NR_BANKS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_X86_MCE_INTEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void mce_intel_feature_init(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void mce_intel_feature_clear(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void cmci_clear(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void cmci_reenable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void cmci_rediscover(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void cmci_recheck(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline void cmci_clear(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline void cmci_reenable(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline void cmci_rediscover(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static inline void cmci_recheck(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int mce_available(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool mce_is_memory_error(struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bool mce_is_correctable(struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int mce_usable_address(struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DECLARE_PER_CPU(unsigned, mce_exception_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DECLARE_PER_CPU(unsigned, mce_poll_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) enum mcp_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	MCP_UC		= BIT(1),	/* log uncorrected errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	MCP_QUEUE_LOG	= BIT(3),	/* only queue to genpool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int mce_notify_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DECLARE_PER_CPU(struct mce, injectm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Disable CMCI/polling for MCA bank claimed by firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) extern void mce_disable_bank(int bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * Exception handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void do_machine_check(struct pt_regs *pt_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * Threshold handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extern void (*mce_threshold_vector)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Deferred error interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) extern void (*deferred_error_int_vector)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * Thermal handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void intel_init_thermal(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Interrupt Handler for core thermal thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) extern int (*platform_thermal_notify)(__u64 msr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Interrupt Handler for package thermal thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) extern int (*platform_thermal_package_notify)(__u64 msr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Callback support of rate control, return true, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * callback has rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) extern bool (*platform_thermal_package_rate_control)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #ifdef CONFIG_X86_THERMAL_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) extern void mcheck_intel_therm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline void mcheck_intel_therm_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * Used by APEI to report memory error via /dev/mcelog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct cper_sec_mem_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) extern void apei_mce_report_mem_error(int corrected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 				      struct cper_sec_mem_err *mem_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * Enumerate new IP types and HWID values in AMD processors which support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * Scalable MCA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #ifdef CONFIG_X86_MCE_AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* These may be used by multiple smca_hwid_mcatypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum smca_bank_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	SMCA_LS = 0,	/* Load Store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	SMCA_LS_V2,	/* Load Store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	SMCA_IF,	/* Instruction Fetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	SMCA_L2_CACHE,	/* L2 Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	SMCA_DE,	/* Decoder Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	SMCA_RESERVED,	/* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	SMCA_EX,	/* Execution Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	SMCA_FP,	/* Floating Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	SMCA_L3_CACHE,	/* L3 Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	SMCA_CS,	/* Coherent Slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	SMCA_CS_V2,	/* Coherent Slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	SMCA_PIE,	/* Power, Interrupts, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	SMCA_UMC,	/* Unified Memory Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	SMCA_PB,	/* Parameter Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	SMCA_PSP,	/* Platform Security Processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	SMCA_PSP_V2,	/* Platform Security Processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	SMCA_SMU,	/* System Management Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	SMCA_SMU_V2,	/* System Management Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	SMCA_MP5,	/* Microprocessor 5 Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	SMCA_NBIO,	/* Northbridge IO Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	SMCA_PCIE,	/* PCI Express Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	N_SMCA_BANK_TYPES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct smca_hwid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	unsigned int bank_type;	/* Use with smca_bank_types for easy indexing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u32 hwid_mcatype;	/* (hwid,mcatype) tuple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u8 count;		/* Number of instances. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct smca_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct smca_hwid *hwid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u32 id;			/* Value of MCA_IPID[InstanceId]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	u8 sysfs_id;		/* Value used for sysfs name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) extern struct smca_bank smca_banks[MAX_NR_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) extern const char *smca_get_long_name(enum smca_bank_types t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) extern bool amd_mce_is_memory_error(struct mce *m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) extern int mce_threshold_create_device(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) extern int mce_threshold_remove_device(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void mce_amd_feature_init(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)	{ return -EINVAL; };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)	{ return mce_amd_feature_init(c); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif /* _ASM_X86_MCE_H */