^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Machine dependent access functions for RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef _ASM_X86_MC146818RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define _ASM_X86_MC146818RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef RTC_PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTC_PORT(x) (0x70 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #if defined(CONFIG_X86_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This lock provides nmi access to the CMOS/RTC registers. It has some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * special properties. It is owned by a CPU and stores the index register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * currently being accessed (if owned). The idea here is that it works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * like a normal lock (normally). However, in an NMI, the NMI code will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * first check to see if its CPU owns the lock, meaning that the NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * interrupted during the read/write of the device. If it does, it goes ahead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * and performs the access and then restores the index register. If it does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * not, it locks normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Note that since we are working with NMIs, we need this lock even in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * a non-SMP machine just to mark that the lock is owned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * This only works with compare-and-swap. There is no other way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * atomically claim the lock and set the owner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern volatile unsigned long cmos_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * All of these below must be called with interrupts off, preempt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * disabled, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void lock_cmos(unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) new = ((smp_processor_id() + 1) << 8) | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (cmos_lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (__cmpxchg(&cmos_lock, 0, new, sizeof(cmos_lock)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline void unlock_cmos(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cmos_lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline int do_i_have_lock_cmos(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return (cmos_lock >> 8) == (smp_processor_id() + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline unsigned char current_lock_cmos_reg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return cmos_lock & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define lock_cmos_prefix(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long cmos_flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) local_irq_save(cmos_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) lock_cmos(reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define lock_cmos_suffix(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unlock_cmos(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) local_irq_restore(cmos_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define lock_cmos_prefix(reg) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define lock_cmos_suffix(reg) do {} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define lock_cmos(reg) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define unlock_cmos() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define do_i_have_lock_cmos() 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define current_lock_cmos_reg() 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * The yet supported machines all access the RTC index register via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * an ISA port access but the way to access the date register differs ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMOS_READ(addr) rtc_cmos_read(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMOS_WRITE(val, addr) rtc_cmos_write(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned char rtc_cmos_read(unsigned char addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void rtc_cmos_write(unsigned char val, unsigned char addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extern int mach_set_rtc_mmss(const struct timespec64 *now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern void mach_get_cmos_time(struct timespec64 *now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RTC_IRQ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* _ASM_X86_MC146818RTC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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