^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * intel-mid.h: Intel MID specific setup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _ASM_X86_INTEL_MID_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _ASM_X86_INTEL_MID_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sfi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern int intel_mid_pci_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) extern void intel_mid_pwr_power_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define INTEL_MID_PWR_LSS_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define INTEL_MID_PWR_LSS_TYPE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern int get_gpio_by_name(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern int sfi_mrtc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern struct sfi_rtc_table_entry sfi_mrtc_array[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Here defines the array of devices platform data that IAFW would export
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * through SFI "DEVS" table, we use name and type to match the device and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * its platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct devs_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) char name[SFI_NAME_LEN + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 msic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void *(*get_platform_data)(void *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define sfi_device(i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __section(".x86_intel_mid_dev.init") = &i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * struct mid_sd_board_info - template for SD device creation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @name: identifies the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @bus_num: board-specific identifier for a given SD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @max_clk: the maximum frequency device supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @platform_data: the particular data stored there is driver-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mid_sd_board_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) char name[SFI_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned short addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 max_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void *platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Medfield is the follow-up of Moorestown, it combines two chip solution into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * one. Other than that it also added always-on and constant tsc and lapic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * timers. Medfield is the platform name, and the chip name is called Penwell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * identified via MSRs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum intel_mid_cpu_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 1 was Moorestown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) INTEL_MID_CPU_CHIP_PENWELL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) INTEL_MID_CPU_CHIP_CLOVERVIEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) INTEL_MID_CPU_CHIP_TANGIER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef CONFIG_X86_INTEL_MID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return __intel_mid_cpu_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline bool intel_mid_has_msic(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern void intel_scu_devices_create(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern void intel_scu_devices_destroy(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #else /* !CONFIG_X86_INTEL_MID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define intel_mid_identify_cpu() 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define intel_mid_has_msic() 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline void intel_scu_devices_create(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline void intel_scu_devices_destroy(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* !CONFIG_X86_INTEL_MID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum intel_mid_timer_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) INTEL_MID_TIMER_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) INTEL_MID_TIMER_APBT_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) INTEL_MID_TIMER_LAPIC_APBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern enum intel_mid_timer_options intel_mid_timer_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Bus Select SoC Fuse value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BSEL_SOC_FUSE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* FSB 133MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BSEL_SOC_FUSE_001 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* FSB 100MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BSEL_SOC_FUSE_101 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* FSB 83MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BSEL_SOC_FUSE_111 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SFI_MTMR_MAX_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SFI_MRTC_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* VRTC timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MRST_VRTC_MAP_SZ 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* #define MRST_VRTC_PGOFFSET 0xc00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern void intel_mid_rtc_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* The offset for the mapping of global gpio pin to irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define INTEL_MID_IRQ_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif /* _ASM_X86_INTEL_MID_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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