Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _ASM_X86_INSN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _ASM_X86_INSN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * x86 instruction analysis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) IBM Corporation, 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* insn_attr_t is defined in inat.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/inat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) struct insn_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 		insn_value_t value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		insn_byte_t bytes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	/* !0 if we've run insn_get_xxx() for this field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	unsigned char got;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	unsigned char nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct insn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct insn_field prefixes;	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 					 * Prefixes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 					 * prefixes.bytes[3]: last prefix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct insn_field rex_prefix;	/* REX prefix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct insn_field vex_prefix;	/* VEX prefix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct insn_field opcode;	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 					 * opcode.bytes[0]: opcode1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 					 * opcode.bytes[1]: opcode2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 					 * opcode.bytes[2]: opcode3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 					 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct insn_field modrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct insn_field sib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct insn_field displacement;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		struct insn_field immediate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		struct insn_field moffset1;	/* for 64bit MOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		struct insn_field immediate1;	/* for 64bit imm or off16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		struct insn_field moffset2;	/* for 64bit MOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		struct insn_field immediate2;	/* for 64bit imm or seg16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int	emulate_prefix_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	insn_attr_t attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned char opnd_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned char addr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned char length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned char x86_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	const insn_byte_t *kaddr;	/* kernel address of insn to analyze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	const insn_byte_t *end_kaddr;	/* kernel address of last insn in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	const insn_byte_t *next_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MAX_INSN_SIZE	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define X86_MODRM_RM(modrm) ((modrm) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define X86_SIB_BASE(sib) ((sib) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define X86_REX_W(rex) ((rex) & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define X86_REX_R(rex) ((rex) & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define X86_REX_X(rex) ((rex) & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define X86_REX_B(rex) ((rex) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* VEX bit flags  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define X86_VEX_W(vex)	((vex) & 0x80)	/* VEX3 Byte2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define X86_VEX_R(vex)	((vex) & 0x80)	/* VEX2/3 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define X86_VEX_X(vex)	((vex) & 0x40)	/* VEX3 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define X86_VEX_B(vex)	((vex) & 0x20)	/* VEX3 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define X86_VEX_L(vex)	((vex) & 0x04)	/* VEX3 Byte2, VEX2 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* VEX bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define X86_EVEX_M(vex)	((vex) & 0x03)		/* EVEX Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define X86_VEX3_M(vex)	((vex) & 0x1f)		/* VEX3 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define X86_VEX2_M	1			/* VEX2.M always 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define X86_VEX_V(vex)	(((vex) & 0x78) >> 3)	/* VEX3 Byte2, VEX2 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define X86_VEX_P(vex)	((vex) & 0x03)		/* VEX3 Byte2, VEX2 Byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define X86_VEX_M_MAX	0x1f			/* VEX3.M Maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) extern void insn_get_prefixes(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) extern void insn_get_opcode(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) extern void insn_get_modrm(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) extern void insn_get_sib(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) extern void insn_get_displacement(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) extern void insn_get_immediate(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) extern void insn_get_length(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* Attribute will be determined after getting ModRM (for opcode groups) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static inline void insn_get_attribute(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	insn_get_modrm(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Instruction uses RIP-relative addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) extern int insn_rip_relative(struct insn *insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Init insn for kernel text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void kernel_insn_init(struct insn *insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				    const void *kaddr, int buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	insn_init(insn, kaddr, buf_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #else /* CONFIG_X86_32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	insn_init(insn, kaddr, buf_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline int insn_is_avx(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (!insn->prefixes.got)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		insn_get_prefixes(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return (insn->vex_prefix.value != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline int insn_is_evex(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (!insn->prefixes.got)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		insn_get_prefixes(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return (insn->vex_prefix.nbytes == 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline int insn_has_emulate_prefix(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return !!insn->emulate_prefix_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Ensure this instruction is decoded completely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline int insn_complete(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return insn->opcode.got && insn->modrm.got && insn->sib.got &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		insn->displacement.got && insn->immediate.got;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return X86_VEX2_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	else if (insn->vex_prefix.nbytes == 3)	/* 3 bytes VEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return X86_VEX3_M(insn->vex_prefix.bytes[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	else					/* EVEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return X86_EVEX_M(insn->vex_prefix.bytes[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return X86_VEX_P(insn->vex_prefix.bytes[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return X86_VEX_P(insn->vex_prefix.bytes[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Get the last prefix id from last prefix or VEX prefix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static inline int insn_last_prefix_id(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (insn_is_avx(insn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return insn_vex_p_bits(insn);	/* VEX_p is a SIMD prefix id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (insn->prefixes.bytes[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Offset of each field from kaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline int insn_offset_rex_prefix(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return insn->prefixes.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline int insn_offset_vex_prefix(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline int insn_offset_opcode(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline int insn_offset_modrm(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return insn_offset_opcode(insn) + insn->opcode.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline int insn_offset_sib(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return insn_offset_modrm(insn) + insn->modrm.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline int insn_offset_displacement(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return insn_offset_sib(insn) + insn->sib.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline int insn_offset_immediate(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return insn_offset_displacement(insn) + insn->displacement.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * for_each_insn_prefix() -- Iterate prefixes in the instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * @insn: Pointer to struct insn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * @idx:  Index storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * @prefix: Prefix byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * and the index is stored in @idx (note that this @idx is just for a cursor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * do not change it.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * Since prefixes.nbytes can be bigger than 4 if some prefixes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * are repeated, it cannot be used for looping over the prefixes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define for_each_insn_prefix(insn, idx, prefix)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define POP_SS_OPCODE 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MOV_SREG_OPCODE 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * Intel SDM Vol.3A 6.8.3 states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * "Any single-step trap that would be delivered following the MOV to SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * suppressed."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * This function returns true if @insn is MOV SS or POP SS. On these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * instructions, single stepping is suppressed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline int insn_masking_exception(struct insn *insn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return insn->opcode.bytes[0] == POP_SS_OPCODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		(insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif /* _ASM_X86_INSN_H */