Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * imr.h: Isolated Memory Region API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright(c) 2013 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright(c) 2015 Bryan O'Donoghue <pure.logic@nexus-software.ie>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _IMR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _IMR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * IMR agent access mask bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * See section 12.7.4.7 from quark-x1000-datasheet.pdf for register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMR_ESRAM_FLUSH		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMR_CPU_SNOOP		BIT(30)		/* Applicable only to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMR_RMU			BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMR_VC1_SAI_ID3		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMR_VC1_SAI_ID2		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMR_VC1_SAI_ID1		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMR_VC1_SAI_ID0		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMR_VC0_SAI_ID3		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMR_VC0_SAI_ID2		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMR_VC0_SAI_ID1		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMR_VC0_SAI_ID0		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMR_CPU_0		BIT(1)		/* SMM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMR_CPU			BIT(0)		/* Non SMM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMR_ACCESS_NONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * Read/Write access-all bits here include some reserved bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * These are the values firmware uses and are accepted by hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * The kernel defines read/write access-all in the same way as firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * in order to have a consistent and crisp definition across firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * bootloader and kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMR_READ_ACCESS_ALL	0xBFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMR_WRITE_ACCESS_ALL	0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Number of IMRs provided by Quark X1000 SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QUARK_X1000_IMR_MAX	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QUARK_X1000_IMR_REGBASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* IMR alignment bits - only bits 31:10 are checked for IMR validity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMR_ALIGN		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMR_MASK		(IMR_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int imr_add_range(phys_addr_t base, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		  unsigned int rmask, unsigned int wmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int imr_remove_range(phys_addr_t base, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif /* _IMR_H */