Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_X86_I8259_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_X86_I8259_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) extern unsigned int cached_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __byte(x, y)		(((unsigned char *)&(y))[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define cached_master_mask	(__byte(0, cached_irq_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define cached_slave_mask	(__byte(1, cached_irq_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* i8259A PIC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PIC_MASTER_CMD		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PIC_MASTER_IMR		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PIC_MASTER_ISR		PIC_MASTER_CMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PIC_MASTER_POLL		PIC_MASTER_ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PIC_MASTER_OCW3		PIC_MASTER_ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIC_SLAVE_CMD		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIC_SLAVE_IMR		0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* i8259A PIC related value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIC_CASCADE_IR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MASTER_ICW4_DEFAULT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLAVE_ICW4_DEFAULT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PIC_ICW4_AEOI		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern raw_spinlock_t i8259A_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* the PIC may need a careful delay on some platforms, hence specific calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline unsigned char inb_pic(unsigned int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	unsigned char value = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 * delay for some accesses to PIC on motherboard or in chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * must be at least one microsecond, so be safe here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void outb_pic(unsigned char value, unsigned int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	outb(value, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	 * delay for some accesses to PIC on motherboard or in chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	 * must be at least one microsecond, so be safe here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern struct irq_chip i8259A_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct legacy_pic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	int nr_legacy_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	void (*mask)(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	void (*unmask)(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	void (*mask_all)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	void (*restore_mask)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	void (*init)(int auto_eoi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	int (*probe)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	int (*irq_pending)(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	void (*make_irq)(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern struct legacy_pic *legacy_pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern struct legacy_pic null_legacy_pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline bool has_legacy_pic(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	return legacy_pic != &null_legacy_pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline int nr_legacy_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	return legacy_pic->nr_legacy_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif /* _ASM_X86_I8259_H */