^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_X86_GART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_X86_GART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/e820/api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) extern void set_up_gart_resume(u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) extern int fallback_aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extern int fallback_aper_force;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) extern int fix_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* PTE bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GPTE_VALID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GPTE_COHERENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Aperture control register bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GARTEN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DISGARTCPU (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DISGARTIO (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DISTLBWALKPRB (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* GART cache control register bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INVGART (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GARTPTEERR (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* K8 On-cpu GART registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AMD64_GARTAPERTURECTL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AMD64_GARTAPERTUREBASE 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AMD64_GARTTABLEBASE 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AMD64_GARTCACHECTL 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef CONFIG_GART_IOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) extern int gart_iommu_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern int gart_iommu_aperture_allowed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern int gart_iommu_aperture_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern void early_gart_iommu_check(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern int gart_iommu_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern void __init gart_parse_options(char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern int gart_iommu_hole_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define gart_iommu_aperture 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define gart_iommu_aperture_allowed 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define gart_iommu_aperture_disabled 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void early_gart_iommu_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline void gart_parse_options(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline int gart_iommu_hole_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) extern int agp_amd64_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Don't enable translation but enable GART IO and CPU accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Also, set DISTLBWALKPRB since GART tables memory is UC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ctl = order << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 tmp, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* address of the mappings table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) addr >>= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp = (u32) addr<<4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tmp &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Enable GART translation for this hammer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ctl |= GARTEN | DISTLBWALKPRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ctl &= ~(DISGARTCPU | DISGARTIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!aper_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (aper_base + aper_size > 0x100000000ULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (aper_size < min_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) aper_size>>20, min_size>>20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif /* _ASM_X86_GART_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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