^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_X86_DESC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_X86_DESC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/desc_defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/ldt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/irq_vectors.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/cpu_entry_area.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) desc->limit0 = info->limit & 0x0ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) desc->base0 = (info->base_addr & 0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) desc->type = (info->read_exec_only ^ 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) desc->type |= info->contents << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Set the ACCESS bit so it can be mapped RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) desc->type |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) desc->s = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) desc->dpl = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) desc->p = info->seg_not_present ^ 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) desc->limit1 = (info->limit & 0xf0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) desc->avl = info->useable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) desc->d = info->seg_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) desc->g = info->limit_in_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) desc->base2 = (info->base_addr & 0xff000000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Don't allow setting of the lm bit. It would confuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * user_64bit_mode and would get overridden by sysret anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) desc->l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct gdt_page {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct desc_struct gdt[GDT_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } __attribute__((aligned(PAGE_SIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Provide the original GDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return per_cpu(gdt_page, cpu).gdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Provide the current original GDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline struct desc_struct *get_current_gdt_rw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return this_cpu_ptr(&gdt_page)->gdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Provide the fixmap address of the remapped GDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Provide the current read-only GDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline struct desc_struct *get_current_gdt_ro(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return get_cpu_gdt_ro(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Provide the physical address of the GDT page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned dpl, unsigned ist, unsigned seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gate->offset_low = (u16) func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) gate->bits.p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) gate->bits.dpl = dpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) gate->bits.zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) gate->bits.type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) gate->offset_middle = (u16) (func >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gate->segment = __KERNEL_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) gate->bits.ist = ist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) gate->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) gate->offset_high = (u32) (func >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) gate->segment = seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) gate->bits.ist = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline int desc_empty(const void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const u32 *desc = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return !(desc[0] | desc[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_PARAVIRT_XXL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include <asm/paravirt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define load_TR_desc() native_load_tr_desc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define load_gdt(dtr) native_load_gdt(dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define load_idt(dtr) native_load_idt(dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define store_gdt(dtr) native_store_gdt(dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define store_tr(tr) (tr = native_store_tr())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define load_TLS(t, cpu) native_load_tls(t, cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define set_ldt native_set_ldt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif /* CONFIG_PARAVIRT_XXL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) memcpy(&idt[entry], gate, sizeof(*gate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) memcpy(&ldt[entry], desc, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case DESC_TSS: size = sizeof(tss_desc); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case DESC_LDT: size = sizeof(ldt_desc); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) default: size = sizeof(*gdt); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) memcpy(&gdt[entry], desc, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline void set_tssldt_descriptor(void *d, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned type, unsigned size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct ldttss_desc *desc = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) memset(desc, 0, sizeof(*desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) desc->limit0 = (u16) size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) desc->base0 = (u16) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) desc->base1 = (addr >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) desc->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) desc->p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) desc->limit1 = (size >> 16) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) desc->base2 = (addr >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) desc->base3 = (u32) (addr >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct desc_struct *d = get_cpu_gdt_rw(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tss_desc tss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __KERNEL_TSS_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) write_gdt_entry(d, entry, &tss, DESC_TSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline void native_set_ldt(const void *addr, unsigned int entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (likely(entries == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) asm volatile("lldt %w0"::"q" (0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ldt_desc ldt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) entries * LDT_ENTRY_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) &ldt, DESC_LDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline void native_load_gdt(const struct desc_ptr *dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) asm volatile("lgdt %0"::"m" (*dtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static __always_inline void native_load_idt(const struct desc_ptr *dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) asm volatile("lidt %0"::"m" (*dtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline void native_store_gdt(struct desc_ptr *dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) asm volatile("sgdt %0":"=m" (*dtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void store_idt(struct desc_ptr *dtr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) asm volatile("sidt %0":"=m" (*dtr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * a read-only remapping. To prevent a page fault, the GDT is switched to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * original writeable version when needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline void native_load_tr_desc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct desc_ptr gdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int cpu = raw_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bool restore = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct desc_struct *fixmap_gdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) native_store_gdt(&gdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) fixmap_gdt = get_cpu_gdt_ro(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * If the current GDT is the read-only fixmap, swap to the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * writeable version. Swap back at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (gdt.address == (unsigned long)fixmap_gdt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) load_direct_gdt(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) restore = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) load_fixmap_gdt(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void native_load_tr_desc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline unsigned long native_store_tr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) asm volatile("str %0":"=r" (tr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_PER_CPU(bool, __tss_limit_invalid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void force_reload_TR(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct desc_struct *d = get_current_gdt_rw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tss_desc tss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * LTR requires an available TSS, and the TSS is currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * busy. Make it be available so that LTR will work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tss.type = DESC_TSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) load_TR_desc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) this_cpu_write(__tss_limit_invalid, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Call this if you need the TSS limit to be correct, which should be the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * if and only if you have TIF_IO_BITMAP set or you're switching to a task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * with TIF_IO_BITMAP set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline void refresh_tss_limit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DEBUG_LOCKS_WARN_ON(preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (unlikely(this_cpu_read(__tss_limit_invalid)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) force_reload_TR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * If you do something evil that corrupts the cached TSS limit (I'm looking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * at you, VMX exits), call this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * The optimization here is that the TSS limit only matters for Linux if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * IO bitmap is in use. If the TSS limit gets forced to its minimum value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * everything works except that IO bitmap will be ignored and all CPL 3 IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * instructions will #GP, which is exactly what we want for normal tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline void invalidate_tss_limit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DEBUG_LOCKS_WARN_ON(preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) force_reload_TR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) this_cpu_write(__tss_limit_invalid, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* This intentionally ignores lm, since 32-bit apps don't have that field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define LDT_empty(info) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ((info)->base_addr == 0 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (info)->limit == 0 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (info)->contents == 0 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (info)->read_exec_only == 1 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (info)->seg_32bit == 0 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (info)->limit_in_pages == 0 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (info)->seg_not_present == 1 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (info)->useable == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static inline bool LDT_zero(const struct user_desc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return (info->base_addr == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) info->limit == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) info->contents == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) info->read_exec_only == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) info->seg_32bit == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) info->limit_in_pages == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) info->seg_not_present == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) info->useable == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static inline void clear_LDT(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) set_ldt(NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline unsigned long get_desc_base(const struct desc_struct *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) desc->base0 = base & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) desc->base1 = (base >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) desc->base2 = (base >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline unsigned long get_desc_limit(const struct desc_struct *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return desc->limit0 | (desc->limit1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) desc->limit0 = limit & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) desc->limit1 = (limit >> 16) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void alloc_intr_gate(unsigned int n, const void *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline void init_idt_data(struct idt_data *data, unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) BUG_ON(n > 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) memset(data, 0, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) data->vector = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) data->segment = __KERNEL_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) data->bits.type = GATE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) data->bits.p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long addr = (unsigned long) d->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) gate->offset_low = (u16) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gate->segment = (u16) d->segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) gate->bits = d->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gate->offset_middle = (u16) (addr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gate->offset_high = (u32) (addr >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gate->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) extern unsigned long system_vectors[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) extern void load_current_idt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) extern void idt_setup_early_handler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) extern void idt_setup_early_traps(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) extern void idt_setup_traps(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) extern void idt_setup_apic_and_irq_gates(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) extern bool idt_is_f00f_address(unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) extern void idt_setup_early_pf(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) extern void idt_setup_ist_traps(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static inline void idt_setup_early_pf(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static inline void idt_setup_ist_traps(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) extern void idt_invalidate(void *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif /* _ASM_X86_DESC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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