Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _ASM_X86_APICDEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _ASM_X86_APICDEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Alan Cox <Alan.Cox@linux.org>, 1995.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define IO_APIC_DEFAULT_PHYS_BASE	0xfec00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define	APIC_DEFAULT_PHYS_BASE		0xfee00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * This is the IO-APIC register space as specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * by Intel docs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IO_APIC_SLOT_SIZE		1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define	APIC_ID		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	APIC_LVR	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define		APIC_LVR_MASK		0xFF00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define		APIC_LVR_DIRECTED_EOI	(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define		GET_APIC_VERSION(x)	((x) & 0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		GET_APIC_MAXLVT(x)	(((x) >> 16) & 0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #  define	APIC_INTEGRATED(x)	((x) & 0xF0u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #  define	APIC_INTEGRATED(x)	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		APIC_XAPIC(x)		((x) >= 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		APIC_EXT_SPACE(x)	((x) & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	APIC_TASKPRI	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define		APIC_TPRI_MASK		0xFFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	APIC_ARBPRI	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define		APIC_ARBPRI_MASK	0xFFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	APIC_PROCPRI	0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	APIC_EOI	0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		APIC_EOI_ACK		0x0 /* Docs say 0 for future compat. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	APIC_RRR	0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	APIC_LDR	0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define		APIC_LDR_MASK		(0xFFu << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define		GET_APIC_LOGICAL_ID(x)	(((x) >> 24) & 0xFFu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define		SET_APIC_LOGICAL_ID(x)	(((x) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define		APIC_ALL_CPUS		0xFFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	APIC_DFR	0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define		APIC_DFR_CLUSTER		0x0FFFFFFFul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define		APIC_DFR_FLAT			0xFFFFFFFFul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	APIC_SPIV	0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define		APIC_SPIV_DIRECTED_EOI		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define		APIC_SPIV_FOCUS_DISABLED	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define		APIC_SPIV_APIC_ENABLED		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	APIC_ISR	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	APIC_TMR	0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	APIC_IRR	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define	APIC_ESR	0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define		APIC_ESR_SEND_CS	0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define		APIC_ESR_RECV_CS	0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define		APIC_ESR_SEND_ACC	0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define		APIC_ESR_RECV_ACC	0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define		APIC_ESR_SENDILL	0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define		APIC_ESR_RECVILL	0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define		APIC_ESR_ILLREGA	0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define 	APIC_LVTCMCI	0x2f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	APIC_ICR	0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define		APIC_DEST_SELF		0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define		APIC_DEST_ALLINC	0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define		APIC_DEST_ALLBUT	0xC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define		APIC_ICR_RR_MASK	0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define		APIC_ICR_RR_INVALID	0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define		APIC_ICR_RR_INPROG	0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define		APIC_ICR_RR_VALID	0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define		APIC_INT_LEVELTRIG	0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define		APIC_INT_ASSERT		0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define		APIC_ICR_BUSY		0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define		APIC_DEST_LOGICAL	0x00800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define		APIC_DEST_PHYSICAL	0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define		APIC_DM_FIXED		0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define		APIC_DM_FIXED_MASK	0x00700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define		APIC_DM_LOWEST		0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define		APIC_DM_SMI		0x00200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define		APIC_DM_REMRD		0x00300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define		APIC_DM_NMI		0x00400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define		APIC_DM_INIT		0x00500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define		APIC_DM_STARTUP		0x00600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define		APIC_DM_EXTINT		0x00700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define		APIC_VECTOR_MASK	0x000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	APIC_ICR2	0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define		GET_APIC_DEST_FIELD(x)	(((x) >> 24) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define		SET_APIC_DEST_FIELD(x)	((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	APIC_LVTT	0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	APIC_LVTTHMR	0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define	APIC_LVTPC	0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	APIC_LVT0	0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define		APIC_LVT_TIMER_BASE_MASK	(0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define		GET_APIC_TIMER_BASE(x)		(((x) >> 18) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define		SET_APIC_TIMER_BASE(x)		(((x) << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define		APIC_TIMER_BASE_CLKIN		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define		APIC_TIMER_BASE_TMBASE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define		APIC_TIMER_BASE_DIV		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define		APIC_LVT_TIMER_ONESHOT		(0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define		APIC_LVT_TIMER_PERIODIC		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define		APIC_LVT_TIMER_TSCDEADLINE	(2 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define		APIC_LVT_MASKED			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define		APIC_LVT_LEVEL_TRIGGER		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define		APIC_LVT_REMOTE_IRR		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define		APIC_INPUT_POLARITY		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define		APIC_SEND_PENDING		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define		APIC_MODE_MASK			0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define		GET_APIC_DELIVERY_MODE(x)	(((x) >> 8) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define		SET_APIC_DELIVERY_MODE(x, y)	(((x) & ~0x700) | ((y) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define			APIC_MODE_FIXED		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define			APIC_MODE_NMI		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define			APIC_MODE_EXTINT	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	APIC_LVT1	0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define	APIC_LVTERR	0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define	APIC_TMICT	0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define	APIC_TMCCT	0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	APIC_TDCR	0x3E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define APIC_SELF_IPI	0x3F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define		APIC_TDR_DIV_TMBASE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define		APIC_TDR_DIV_1		0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define		APIC_TDR_DIV_2		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define		APIC_TDR_DIV_4		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define		APIC_TDR_DIV_8		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define		APIC_TDR_DIV_16		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define		APIC_TDR_DIV_32		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define		APIC_TDR_DIV_64		0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define		APIC_TDR_DIV_128	0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define	APIC_EFEAT	0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	APIC_ECTRL	0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define APIC_EILVTn(n)	(0x500 + 0x10 * n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define		APIC_EILVT_NR_AMD_K8	1	/* # of extended interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define		APIC_EILVT_NR_AMD_10H	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define		APIC_EILVT_MSG_FIX	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define		APIC_EILVT_MSG_SMI	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define		APIC_EILVT_MSG_NMI	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define		APIC_EILVT_MSG_EXT	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define		APIC_EILVT_MASKED	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define APIC_BASE_MSR	0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define XAPIC_ENABLE	(1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define X2APIC_ENABLE	(1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define MAX_IO_APICS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define MAX_LOCAL_APIC 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define MAX_IO_APICS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) # define MAX_LOCAL_APIC 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * All x86-64 systems are xAPIC compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * In the following, "apicid" is a physical APIC ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define XAPIC_DEST_CPUS_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define XAPIC_DEST_CPUS_MASK	((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define XAPIC_DEST_CLUSTER_MASK	(XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define APIC_CLUSTER(apicid)	((apicid) & XAPIC_DEST_CLUSTER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define APIC_CLUSTERID(apicid)	(APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define APIC_CPUID(apicid)	((apicid) & XAPIC_DEST_CPUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define NUM_APIC_CLUSTERS	((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * the local APIC register structure, memory mapped. Not terribly well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * tested, but we might eventually use this one in the future - the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * problem why we cannot use it right now is the P5 APIC, it has an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define u32 unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct local_apic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*000*/	struct { u32 __reserved[4]; } __reserved_01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*010*/	struct { u32 __reserved[4]; } __reserved_02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*020*/	struct { /* APIC ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		u32   __reserved_1	: 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			phys_apic_id	:  4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			__reserved_2	:  4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		u32 __reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	} id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*030*/	const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct { /* APIC Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		u32   version		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			__reserved_1	:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			max_lvt		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			__reserved_2	:  8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		u32 __reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	} version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*040*/	struct { u32 __reserved[4]; } __reserved_03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*050*/	struct { u32 __reserved[4]; } __reserved_04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*060*/	struct { u32 __reserved[4]; } __reserved_05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*070*/	struct { u32 __reserved[4]; } __reserved_06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*080*/	struct { /* Task Priority Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		u32   priority	:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			__reserved_1	: 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	} tpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*090*/	const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct { /* Arbitration Priority Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		u32   priority	:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			__reserved_1	: 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	} apr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*0A0*/	const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct { /* Processor Priority Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		u32   priority	:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			__reserved_1	: 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	} ppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*0B0*/	struct { /* End Of Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		u32   eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		u32 __reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	} eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*0C0*/	struct { u32 __reserved[4]; } __reserved_07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*0D0*/	struct { /* Logical Destination Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		u32   __reserved_1	: 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			logical_dest	:  8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	} ldr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*0E0*/	struct { /* Destination Format Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		u32   __reserved_1	: 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			model		:  4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	} dfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*0F0*/	struct { /* Spurious Interrupt Vector Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		u32	spurious_vector	:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			apic_enabled	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			focus_cpu	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			__reserved_2	: 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		u32 __reserved_3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	} svr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*100*/	struct { /* In Service Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*170*/		u32 bitfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		u32 __reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	} isr [8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*180*/	struct { /* Trigger Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*1F0*/		u32 bitfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		u32 __reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} tmr [8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*200*/	struct { /* Interrupt Request Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*270*/		u32 bitfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		u32 __reserved[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	} irr [8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*280*/	union { /* Error Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			u32   send_cs_error			:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				receive_cs_error		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				send_accept_error		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				receive_accept_error		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				__reserved_1			:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				send_illegal_vector		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				receive_illegal_vector		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				illegal_register_address	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 				__reserved_2			: 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			u32 __reserved_3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		} error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			u32 errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			u32 __reserved_3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		} all_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	} esr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*290*/	struct { u32 __reserved[4]; } __reserved_08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*2A0*/	struct { u32 __reserved[4]; } __reserved_09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*2B0*/	struct { u32 __reserved[4]; } __reserved_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*2C0*/	struct { u32 __reserved[4]; } __reserved_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*2D0*/	struct { u32 __reserved[4]; } __reserved_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*2E0*/	struct { u32 __reserved[4]; } __reserved_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*2F0*/	struct { u32 __reserved[4]; } __reserved_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*300*/	struct { /* Interrupt Command Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		u32   vector			:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			delivery_mode		:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			destination_mode	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			delivery_status		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			__reserved_1		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			level			:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			trigger			:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			__reserved_2		:  2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			shorthand		:  2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			__reserved_3		:  12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		u32 __reserved_4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	} icr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*310*/	struct { /* Interrupt Command Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			u32   __reserved_1	: 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				phys_dest	:  4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				__reserved_2	:  4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			u32   __reserved_3	: 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 				logical_dest	:  8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		} dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		u32 __reserved_4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	} icr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*320*/	struct { /* LVT - Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		u32   vector		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			__reserved_1	:  4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			delivery_status	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			__reserved_2	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			mask		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			timer_mode	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			__reserved_3	: 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		u32 __reserved_4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	} lvt_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*330*/	struct { /* LVT - Thermal Sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		u32  vector		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			delivery_mode	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			__reserved_1	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			delivery_status	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			__reserved_2	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			mask		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			__reserved_3	: 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		u32 __reserved_4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	} lvt_thermal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*340*/	struct { /* LVT - Performance Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		u32   vector		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			delivery_mode	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			__reserved_1	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			delivery_status	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			__reserved_2	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			mask		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			__reserved_3	: 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		u32 __reserved_4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	} lvt_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*350*/	struct { /* LVT - LINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		u32   vector		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			delivery_mode	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			__reserved_1	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			delivery_status	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			polarity	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			remote_irr	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			trigger		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			mask		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			__reserved_2	: 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		u32 __reserved_3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	} lvt_lint0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*360*/	struct { /* LVT - LINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		u32   vector		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			delivery_mode	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			__reserved_1	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			delivery_status	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			polarity	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			remote_irr	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			trigger		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			mask		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			__reserved_2	: 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		u32 __reserved_3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	} lvt_lint1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*370*/	struct { /* LVT - Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		u32   vector		:  8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			__reserved_1	:  4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			delivery_status	:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			__reserved_2	:  3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			mask		:  1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			__reserved_3	: 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		u32 __reserved_4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	} lvt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*380*/	struct { /* Timer Initial Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		u32   initial_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	} timer_icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*390*/	const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct { /* Timer Current Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		u32   curr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	} timer_ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*3A0*/	struct { u32 __reserved[4]; } __reserved_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*3B0*/	struct { u32 __reserved[4]; } __reserved_17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*3C0*/	struct { u32 __reserved[4]; } __reserved_18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*3D0*/	struct { u32 __reserved[4]; } __reserved_19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*3E0*/	struct { /* Timer Divide Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		u32   divisor		:  4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			__reserved_1	: 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		u32 __reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	} timer_dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*3F0*/	struct { u32 __reserved[4]; } __reserved_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #undef u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)  #define BAD_APICID 0xFFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)  #define BAD_APICID 0xFFFFu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum ioapic_irq_destination_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	dest_Fixed		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	dest_LowestPrio		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	dest_SMI		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	dest__reserved_1	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	dest_NMI		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	dest_INIT		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	dest__reserved_2	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	dest_ExtINT		= 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif /* _ASM_X86_APICDEF_H */