^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_X86_APIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_X86_APIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/alternative.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/apicdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mpspec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARCH_APICTIMER_STOPS_ON_C3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Debugging macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APIC_QUIET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define APIC_VERBOSE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APIC_DEBUG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Macros for apic_extnmi which controls external NMI masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APIC_EXTNMI_BSP 0 /* Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define APIC_EXTNMI_ALL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define APIC_EXTNMI_NONE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Define the default level of output to be very little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This can be turned up by using apic=verbose for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * information and apic=debug for _lots_ of information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * apic_verbosity is defined in apic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define apic_printk(v, s, a...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if ((v) <= apic_verbosity) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) printk(s, ##a); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern void generic_apic_probe(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void generic_apic_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_X86_LOCAL_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern int apic_verbosity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) extern int local_apic_timer_c2_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern int disable_apic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern unsigned int lapic_timer_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern enum apic_intr_mode_id apic_intr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum apic_intr_mode_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) APIC_PIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) APIC_VIRTUAL_WIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) APIC_VIRTUAL_WIRE_NO_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) APIC_SYMMETRIC_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) APIC_SYMMETRIC_IO_NO_ROUTING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern void __inquire_remote_apic(int apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #else /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline void __inquire_remote_apic(int apicid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void default_inquire_remote_apic(int apicid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (apic_verbosity >= APIC_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __inquire_remote_apic(apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * With 82489DX we can't rely on apic feature bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * retrieved via cpuid but still have to deal with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * such an apic chip so we assume that SMP configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * is found from MP table (64bit case uses ACPI mostly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * which set smp presence flag as well so we are safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * to use this helper too).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline bool apic_from_smp_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return smp_found_config && !disable_apic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Basic functions accessing APICs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_PARAVIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <asm/paravirt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) extern int setup_profiling_timer(unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void native_apic_mem_write(u32 reg, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ASM_OUTPUT2("=r" (v), "=m" (*addr)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ASM_OUTPUT2("0" (v), "m" (*addr)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline u32 native_apic_mem_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return *((volatile u32 *)(APIC_BASE + reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern void native_apic_wait_icr_idle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern u32 native_safe_apic_wait_icr_idle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) extern void native_apic_icr_write(u32 low, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern u64 native_apic_icr_read(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline bool apic_is_x2apic_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u64 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return msr & X2APIC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern void enable_IR_x2apic(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern int get_physical_broadcast(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern int lapic_get_maxlvt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern void clear_local_APIC(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern void disconnect_bsp_APIC(int virt_wire_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern void disable_local_APIC(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern void apic_soft_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern void lapic_shutdown(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern void sync_Arb_IDs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) extern void init_bsp_APIC(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) extern void apic_intr_mode_select(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) extern void apic_intr_mode_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) extern void init_apic_mappings(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void register_lapic_address(unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) extern void setup_boot_APIC_clock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) extern void setup_secondary_APIC_clock(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern void lapic_update_tsc_freq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline int apic_force_enable(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern int apic_force_enable(unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) extern void apic_ap_setup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * On 32bit this is mach-xxx local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) extern int apic_is_clustered_box(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline int apic_is_clustered_box(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern void lapic_assign_system_vectors(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern void lapic_update_legacy_vectors(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) extern void lapic_online(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) extern void lapic_offline(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) extern bool apic_needs_pit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) extern void apic_send_IPI_allbutself(unsigned int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #else /* !CONFIG_X86_LOCAL_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline void lapic_shutdown(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define local_apic_timer_c2_ok 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void init_apic_mappings(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline void disable_local_APIC(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define setup_boot_APIC_clock x86_init_noop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) # define setup_secondary_APIC_clock x86_init_noop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline void lapic_update_tsc_freq(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void init_bsp_APIC(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline void apic_intr_mode_select(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline void apic_intr_mode_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline void lapic_assign_system_vectors(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline bool apic_needs_pit(void) { return true; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif /* !CONFIG_X86_LOCAL_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #ifdef CONFIG_X86_X2APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline void native_apic_msr_write(u32 reg, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) reg == APIC_LVR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline u32 native_apic_msr_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u64 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (reg == APIC_DFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return (u32)msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline void native_x2apic_wait_icr_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* no need to wait for icr idle in x2apic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline u32 native_safe_x2apic_wait_icr_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* no need to wait for icr idle in x2apic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline void native_x2apic_icr_write(u32 low, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline u64 native_x2apic_icr_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) extern int x2apic_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) extern int x2apic_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) extern void __init x2apic_set_max_apicid(u32 apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) extern void __init check_x2apic(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) extern void x2apic_setup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline int x2apic_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #else /* !CONFIG_X86_X2APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void check_x2apic(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline void x2apic_setup(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline int x2apic_enabled(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define x2apic_mode (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define x2apic_supported() (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif /* !CONFIG_X86_X2APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Copyright 2004 James Cleverdon, IBM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Generic APIC sub-arch data struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Hacked for x86-64 by James Cleverdon from i386 architecture code by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * James Cleverdon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct apic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Hotpath functions first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void (*eoi_write)(u32 reg, u32 v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void (*native_eoi_write)(u32 reg, u32 v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void (*write)(u32 reg, u32 v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 (*read)(u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* IPI related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void (*wait_icr_idle)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 (*safe_wait_icr_idle)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void (*send_IPI)(int cpu, int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void (*send_IPI_mask)(const struct cpumask *mask, int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void (*send_IPI_allbutself)(int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void (*send_IPI_all)(int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void (*send_IPI_self)(int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* dest_logical is used by the IPI functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 dest_logical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 disable_esr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 irq_delivery_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 irq_dest_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 (*calc_dest_apicid)(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* ICR related functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u64 (*icr_read)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void (*icr_write)(u32 low, u32 high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Probe, setup and smpboot functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int (*probe)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int (*apic_id_valid)(u32 apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int (*apic_id_registered)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bool (*check_apicid_used)(physid_mask_t *map, int apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void (*init_apic_ldr)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void (*setup_apic_routing)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int (*cpu_present_to_apicid)(int mps_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int (*check_phys_apicid_present)(int phys_apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int (*phys_pkg_id)(int cpuid_apic, int index_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 (*get_apic_id)(unsigned long x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 (*set_apic_id)(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* wakeup_secondary_cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void (*inquire_remote_apic)(int apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Called very early during boot from get_smp_config(). It should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * return the logical apicid. x86_[bios]_cpu_to_apicid is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * initialized before this function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * If logical apicid can't be determined that early, the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * may return BAD_APICID. Logical apicid will be configured after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * won't be applied properly during early boot in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int (*x86_32_early_logical_apicid)(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Pointer to the local APIC driver in use on this system (there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * always just one such driver in use - the kernel decides via an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * early probing process which one it picks - and then sticks to it):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) extern struct apic *apic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * APIC drivers are probed based on how they are listed in the .apicdrivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * section. So the order is important and enforced by the ordering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * of different apic driver files in the Makefile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * For the files having two apic drivers, we use apic_drivers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * to enforce the order with in them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define apic_driver(sym) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct apic *__apicdrivers_##sym __used \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __aligned(sizeof(struct apic *)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) __section(".apicdrivers") = { &sym }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define apic_drivers(sym1, sym2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct apic *__apicdrivers_##sym1##sym2[2] __used \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) __aligned(sizeof(struct apic *)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __section(".apicdrivers") = { &sym1, &sym2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) extern struct apic *__apicdrivers[], *__apicdrivers_end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * APIC functionality to boot other CPUs - only used on SMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) extern int lapic_can_unplug_cpu(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #ifdef CONFIG_X86_LOCAL_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static inline u32 apic_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return apic->read(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static inline void apic_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) apic->write(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static inline void apic_eoi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static inline u64 apic_icr_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return apic->icr_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline void apic_icr_write(u32 low, u32 high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) apic->icr_write(low, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static inline void apic_wait_icr_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) apic->wait_icr_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static inline u32 safe_apic_wait_icr_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return apic->safe_wait_icr_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #else /* CONFIG_X86_LOCAL_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static inline u32 apic_read(u32 reg) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static inline void apic_write(u32 reg, u32 val) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline void apic_eoi(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static inline u64 apic_icr_read(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static inline void apic_icr_write(u32 low, u32 high) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static inline void apic_wait_icr_idle(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #endif /* CONFIG_X86_LOCAL_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) extern void apic_ack_irq(struct irq_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline void ack_APIC_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * ack_APIC_irq() actually gets compiled as a single instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * ... yummie.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) apic_eoi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static inline bool lapic_vector_set_in_irr(unsigned int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return !!(irr & (1U << (vector % 32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline unsigned default_get_apic_id(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return (x >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return (x >> 24) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Warm reset vector position:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TRAMPOLINE_PHYS_LOW 0x467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define TRAMPOLINE_PHYS_HIGH 0x469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) extern void generic_bigsmp_probe(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #ifdef CONFIG_X86_LOCAL_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define APIC_DFR_VALUE (APIC_DFR_FLAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) extern struct apic apic_noop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static inline unsigned int read_apic_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int reg = apic_read(APIC_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return apic->get_apic_id(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) extern int default_apic_id_valid(u32 apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) extern int default_acpi_madt_oem_check(char *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) extern void default_setup_apic_routing(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) extern u32 apic_default_calc_apicid(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) extern u32 apic_flat_calc_apicid(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) extern int default_cpu_present_to_apicid(int mps_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) extern int default_check_phys_apicid_present(int phys_apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #endif /* CONFIG_X86_LOCAL_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool apic_id_is_primary_thread(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void apic_smt_update(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static inline void apic_smt_update(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct msi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) # define x86_vector_msi_compose_msg NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) extern void ioapic_zap_locks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #endif /* _ASM_X86_APIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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