Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Hyper-V specific APIC code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2018, Microsoft, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author : K. Y. Srinivasan <kys@microsoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * under the terms of the GNU General Public License version 2 as published
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * NON INFRINGEMENT.  See the GNU General Public License for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/hyperv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/cpuhotplug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/hypervisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/mshyperv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <asm/trace/hyperv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static struct apic orig_apic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static u64 hv_apic_icr_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u64 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	rdmsrl(HV_X64_MSR_ICR, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void hv_apic_icr_write(u32 low, u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u64 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	reg_val = SET_APIC_DEST_FIELD(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	reg_val = reg_val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	reg_val |= low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	wrmsrl(HV_X64_MSR_ICR, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static u32 hv_apic_read(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 reg_val, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	case APIC_EOI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		rdmsr(HV_X64_MSR_EOI, reg_val, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case APIC_TASKPRI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		rdmsr(HV_X64_MSR_TPR, reg_val, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return native_apic_mem_read(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void hv_apic_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	case APIC_EOI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		wrmsr(HV_X64_MSR_EOI, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case APIC_TASKPRI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		wrmsr(HV_X64_MSR_TPR, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		native_apic_mem_write(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void hv_apic_eoi_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	wrmsr(HV_X64_MSR_EOI, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * IPI implementation on Hyper-V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct hv_send_ipi_ex **arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct hv_send_ipi_ex *ipi_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	int nr_bank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ipi_arg = *arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (unlikely(!ipi_arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		goto ipi_mask_ex_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ipi_arg->vector = vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ipi_arg->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ipi_arg->vp_set.valid_bank_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (!cpumask_equal(mask, cpu_present_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (nr_bank < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		goto ipi_mask_ex_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (!nr_bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			      ipi_arg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ipi_mask_ex_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return ((ret == 0) ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static bool __send_ipi_mask(const struct cpumask *mask, int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int cur_cpu, vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct hv_send_ipi ipi_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	trace_hyperv_send_ipi_mask(mask, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (cpumask_empty(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (!hv_hypercall_pg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 * From the supplied CPU set we need to figure out if we can get away
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * highest VP number in the set is < 64. As VP numbers are usually in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * ascending order and match Linux CPU ids, here is an optimization:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 * we check the VP number for the highest bit in the supplied set first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * a must. We will also check all VP numbers when walking the supplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * CPU set to remain correct in all cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		goto do_ex_hypercall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ipi_arg.vector = vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ipi_arg.cpu_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	for_each_cpu(cur_cpu, mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		vcpu = hv_cpu_number_to_vp_number(cur_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (vcpu == VP_INVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		 * This particular version of the IPI hypercall can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		 * only target upto 64 CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (vcpu >= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			goto do_ex_hypercall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		__set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				     ipi_arg.cpu_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return ((ret == 0) ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) do_ex_hypercall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return __send_ipi_mask_ex(mask, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static bool __send_ipi_one(int cpu, int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int vp = hv_cpu_number_to_vp_number(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	trace_hyperv_send_ipi_one(cpu, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (!hv_hypercall_pg || (vp == VP_INVAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (vp >= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return __send_ipi_mask_ex(cpumask_of(cpu), vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return !hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void hv_send_ipi(int cpu, int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!__send_ipi_one(cpu, vector))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		orig_apic.send_IPI(cpu, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!__send_ipi_mask(mask, vector))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		orig_apic.send_IPI_mask(mask, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	unsigned int this_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct cpumask new_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	const struct cpumask *local_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	cpumask_copy(&new_mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	cpumask_clear_cpu(this_cpu, &new_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	local_mask = &new_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!__send_ipi_mask(local_mask, vector))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		orig_apic.send_IPI_mask_allbutself(mask, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void hv_send_ipi_allbutself(int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void hv_send_ipi_all(int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!__send_ipi_mask(cpu_online_mask, vector))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		orig_apic.send_IPI_all(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void hv_send_ipi_self(int vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (!__send_ipi_one(smp_processor_id(), vector))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		orig_apic.send_IPI_self(vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __init hv_apic_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		pr_info("Hyper-V: Using IPI hypercalls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		 * Set the IPI entry points.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		orig_apic = *apic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		apic->send_IPI = hv_send_ipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		apic->send_IPI_mask = hv_send_ipi_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		apic->send_IPI_allbutself = hv_send_ipi_allbutself;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		apic->send_IPI_all = hv_send_ipi_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		apic->send_IPI_self = hv_send_ipi_self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		pr_info("Hyper-V: Using enlightened APIC (%s mode)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			x2apic_enabled() ? "x2apic" : "xapic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		 * When in x2apic mode, don't use the Hyper-V specific APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		 * accessors since the field layout in the ICR register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		 * different in x2apic mode. Furthermore, the architectural
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		 * x2apic MSRs function just as well as the Hyper-V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		 * synthetic APIC MSRs, so there's no benefit in having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		 * separate Hyper-V accessors for x2apic mode. The only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		 * exception is hv_apic_eoi_write, because it benefits from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		 * lazy EOI when available, but the same accessor works for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		 * both xapic and x2apic because the field layout is the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		apic_set_eoi_write(hv_apic_eoi_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (!x2apic_enabled()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			apic->read      = hv_apic_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			apic->write     = hv_apic_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			apic->icr_write = hv_apic_icr_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			apic->icr_read  = hv_apic_icr_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }