^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel(R) Processor Trace PMU driver for perf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013-2014, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Intel PT is specified in the Intel Architecture Instruction Set Extensions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Programming Reference:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * http://software.intel.com/en-us/intel-isa-extensions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __INTEL_PT_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __INTEL_PT_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Single-entry ToPA: when this close to region boundary, switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * buffers to avoid losing data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TOPA_PMI_MARGIN 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TOPA_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline unsigned int sizes(unsigned int tsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return 1 << (tsz + TOPA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct topa_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u64 end : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u64 rsvd0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u64 intr : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u64 rsvd1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u64 stop : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u64 rsvd2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u64 size : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u64 rsvd3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u64 base : 36;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u64 rsvd4 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* TSC to Core Crystal Clock Ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPUID_TSC_LEAF 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct pt_pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool vmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool branch_en_always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long max_nonturbo_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int tsc_art_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int tsc_art_den;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * struct pt_buffer - buffer configuration; one buffer per task_struct or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * cpu, depending on perf event configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @tables: list of ToPA tables in this buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @first: shorthand for first topa table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @last: shorthand for last topa table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @cur: current topa table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @nr_pages: buffer size in pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @cur_idx: current output region's index within @cur table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @output_off: offset within the current output region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @data_size: running total of the amount of data in this buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @lost: if data was lost/truncated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @head: logical write offset inside the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @snapshot: if this is for a snapshot/overwrite counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @single: use Single Range Output instead of ToPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @stop_pos: STOP topa entry index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @intr_pos: INT topa entry index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @stop_te: STOP topa entry pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @intr_te: INT topa entry pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @data_pages: array of pages from perf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @topa_index: table of topa entries indexed by page offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pt_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct list_head tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct topa *first, *last, *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int cur_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) size_t output_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) local_t data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) local64_t head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bool snapshot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool single;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) long stop_pos, intr_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct topa_entry *stop_te, *intr_te;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void **data_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PT_FILTERS_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * struct pt_filter - IP range filter configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @msr_a: range start, goes to RTIT_ADDRn_A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @msr_b: range end, goes to RTIT_ADDRn_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @config: 4-bit field in RTIT_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct pt_filter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long msr_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long msr_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * struct pt_filters - IP range filtering context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @filter: filters defined for this context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @nr_filters: number of defined filters in the @filter array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pt_filters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pt_filter filter[PT_FILTERS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int nr_filters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * struct pt - per-cpu pt context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @handle: perf output handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @filters: last configured filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @handle_nmi: do handle PT PMI on this cpu, there's an active event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @vmx_on: 1 if VMX is ON on this cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @output_base: cached RTIT_OUTPUT_BASE MSR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @output_mask: cached RTIT_OUTPUT_MASK MSR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct perf_output_handle handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pt_filters filters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int handle_nmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int vmx_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u64 output_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u64 output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif /* __INTEL_PT_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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