^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include "../perf_event.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Not sure about some of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static const u64 p6_perfmon_event_map[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const u64 __initconst p6_hw_cache_event_ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [PERF_COUNT_HW_CACHE_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [PERF_COUNT_HW_CACHE_OP_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [PERF_COUNT_HW_CACHE_RESULT_MAX] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [ C(L1D) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [ C(L1I ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [ C(LL ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [ C(DTLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [ C(ITLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [ C(BPU ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static u64 p6_pmu_event_map(int hw_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return p6_perfmon_event_map[hw_event];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Event setting that is specified not to count anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * We use this to effectively disable a counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * L2_RQSTS with 0 MESI unit mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define P6_NOP_EVENT 0x0000002EULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct event_constraint p6_event_constraints[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EVENT_CONSTRAINT_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void p6_pmu_disable_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* p6 only has one enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rdmsrl(MSR_P6_EVNTSEL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wrmsrl(MSR_P6_EVNTSEL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void p6_pmu_enable_all(int added)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* p6 only has one enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) rdmsrl(MSR_P6_EVNTSEL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val |= ARCH_PERFMON_EVENTSEL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) wrmsrl(MSR_P6_EVNTSEL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) p6_pmu_disable_event(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u64 val = P6_NOP_EVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (void)wrmsrl_safe(hwc->config_base, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void p6_pmu_enable_event(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = hwc->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * p6 only has a global event enable, set on PerfEvtSel0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * We "disable" events by programming P6_NOP_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * and we rely on p6_pmu_enable_all() being called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * to actually enable the events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (void)wrmsrl_safe(hwc->config_base, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PMU_FORMAT_ATTR(event, "config:0-7" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PMU_FORMAT_ATTR(umask, "config:8-15" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PMU_FORMAT_ATTR(edge, "config:18" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PMU_FORMAT_ATTR(pc, "config:19" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PMU_FORMAT_ATTR(inv, "config:23" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PMU_FORMAT_ATTR(cmask, "config:24-31" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct attribute *intel_p6_formats_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &format_attr_umask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &format_attr_edge.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &format_attr_pc.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &format_attr_inv.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) &format_attr_cmask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static __initconst const struct x86_pmu p6_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "p6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .handle_irq = x86_pmu_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .disable_all = p6_pmu_disable_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .enable_all = p6_pmu_enable_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .enable = p6_pmu_enable_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .disable = p6_pmu_disable_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .hw_config = x86_pmu_hw_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .schedule_events = x86_schedule_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .eventsel = MSR_P6_EVNTSEL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .perfctr = MSR_P6_PERFCTR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .event_map = p6_pmu_event_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .max_events = ARRAY_SIZE(p6_perfmon_event_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .apic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .max_period = (1ULL << 31) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .version = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .num_counters = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Events have 40 bits implemented. However they are designed such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * that bits [32-39] are sign extensions of bit 31. As such the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * effective width of a event for P6-like PMU is 32 bits only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * See IA-32 Intel Architecture Software developer manual Vol 3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .cntval_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .cntval_mask = (1ULL << 32) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .get_event_constraints = x86_get_event_constraints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .event_constraints = p6_event_constraints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .format_attrs = intel_p6_formats_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .events_sysfs_show = intel_event_sysfs_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static __init void p6_pmu_rdpmc_quirk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (boot_cpu_data.x86_stepping < 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * PPro erratum 26; fixed in stepping 9 and above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) x86_pmu.attr_rdpmc_broken = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) x86_pmu.attr_rdpmc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __init int p6_pmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) x86_pmu = p6_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (boot_cpu_data.x86_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case 1: /* Pentium Pro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) x86_add_quirk(p6_pmu_rdpmc_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 3: /* Pentium II - Klamath */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 5: /* Pentium II - Deschutes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case 6: /* Pentium II - Mendocino */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case 7: /* Pentium III - Katmai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case 8: /* Pentium III - Coppermine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 10: /* Pentium III Xeon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 11: /* Pentium III - Tualatin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case 9: /* Pentium M - Banias */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case 13: /* Pentium M - Dothan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sizeof(hw_cache_event_ids));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags