^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/insn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "../perf_event.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static const enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) LBR_EIP_FLAGS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) LBR_TSX = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Intel LBR_SELECT bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Intel Vol3a, April 2011, Section 16.7 Table 16-10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Hardware branch filter (not available on all CPUs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LBR_JCC_BIT 2 /* do not capture conditional branches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LBR_RETURN_BIT 5 /* do not capture near returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LBR_FAR_BIT 8 /* do not capture far branches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LBR_CALL_STACK_BIT 9 /* enable call stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Following bit only exists in Linux; we mask it out before writing it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * the actual MSR. But it helps the constraint perf code to understand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * that this is a separate configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LBR_USER (1 << LBR_USER_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LBR_JCC (1 << LBR_JCC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LBR_RETURN (1 << LBR_RETURN_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LBR_FAR (1 << LBR_FAR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LBR_PLM (LBR_KERNEL | LBR_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LBR_NOT_SUPP -1 /* LBR filter not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LBR_IGN 0 /* ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LBR_ANY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (LBR_JCC |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) LBR_REL_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) LBR_IND_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) LBR_RETURN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) LBR_REL_JMP |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LBR_IND_JMP |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) LBR_FAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LBR_FROM_FLAG_ABORT BIT_ULL(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * x86control flow change classification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * x86control flow changes include branches, interrupts, traps, faults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) X86_BR_NONE = 0, /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) X86_BR_USER = 1 << 0, /* branch target is user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) X86_BR_CALL = 1 << 2, /* call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) X86_BR_RET = 1 << 3, /* return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) X86_BR_SYSCALL = 1 << 4, /* syscall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) X86_BR_SYSRET = 1 << 5, /* syscall return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) X86_BR_INT = 1 << 6, /* sw interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) X86_BR_IRET = 1 << 7, /* return from interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) X86_BR_JCC = 1 << 8, /* conditional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) X86_BR_JMP = 1 << 9, /* jump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) X86_BR_IND_CALL = 1 << 11,/* indirect calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) X86_BR_ABORT = 1 << 12,/* transaction abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) X86_BR_IN_TX = 1 << 13,/* in transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) X86_BR_NO_TX = 1 << 14,/* not in transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) X86_BR_CALL_STACK = 1 << 16,/* call stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) X86_BR_IND_JMP = 1 << 17,/* indirect jump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define X86_BR_ANY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (X86_BR_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) X86_BR_RET |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) X86_BR_SYSCALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) X86_BR_SYSRET |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) X86_BR_INT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) X86_BR_IRET |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) X86_BR_JCC |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) X86_BR_JMP |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) X86_BR_IRQ |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) X86_BR_ABORT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) X86_BR_IND_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) X86_BR_IND_JMP |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) X86_BR_ZERO_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define X86_BR_ANY_CALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) (X86_BR_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) X86_BR_IND_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) X86_BR_ZERO_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) X86_BR_SYSCALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) X86_BR_IRQ |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) X86_BR_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Intel LBR_CTL bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Hardware branch filter for Arch LBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ARCH_LBR_KERNEL_BIT 1 /* capture at ring0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ARCH_LBR_USER_BIT 2 /* capture at ring > 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ARCH_LBR_CALL_STACK_BIT 3 /* enable call stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ARCH_LBR_JCC_BIT 16 /* capture conditional branches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ARCH_LBR_REL_JMP_BIT 17 /* capture relative jumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ARCH_LBR_IND_JMP_BIT 18 /* capture indirect jumps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ARCH_LBR_REL_CALL_BIT 19 /* capture relative calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ARCH_LBR_IND_CALL_BIT 20 /* capture indirect calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ARCH_LBR_RETURN_BIT 21 /* capture near returns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ARCH_LBR_OTHER_BRANCH_BIT 22 /* capture other branches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ARCH_LBR_KERNEL (1ULL << ARCH_LBR_KERNEL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ARCH_LBR_USER (1ULL << ARCH_LBR_USER_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ARCH_LBR_CALL_STACK (1ULL << ARCH_LBR_CALL_STACK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ARCH_LBR_JCC (1ULL << ARCH_LBR_JCC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ARCH_LBR_REL_JMP (1ULL << ARCH_LBR_REL_JMP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ARCH_LBR_IND_JMP (1ULL << ARCH_LBR_IND_JMP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ARCH_LBR_REL_CALL (1ULL << ARCH_LBR_REL_CALL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ARCH_LBR_IND_CALL (1ULL << ARCH_LBR_IND_CALL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ARCH_LBR_RETURN (1ULL << ARCH_LBR_RETURN_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ARCH_LBR_OTHER_BRANCH (1ULL << ARCH_LBR_OTHER_BRANCH_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ARCH_LBR_ANY \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (ARCH_LBR_JCC |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ARCH_LBR_REL_JMP |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ARCH_LBR_IND_JMP |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ARCH_LBR_REL_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ARCH_LBR_IND_CALL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ARCH_LBR_RETURN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ARCH_LBR_OTHER_BRANCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ARCH_LBR_CTL_MASK 0x7f000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static __always_inline bool is_lbr_call_stack_bit_set(u64 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (static_cpu_has(X86_FEATURE_ARCH_LBR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return !!(config & ARCH_LBR_CALL_STACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return !!(config & LBR_CALL_STACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * otherwise it becomes near impossible to get a reliable stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void __intel_pmu_lbr_enable(bool pmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u64 debugctl, lbr_select = 0, orig_debugctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * No need to unfreeze manually, as v4 can do that as part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * of the GLOBAL_STATUS ack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (pmi && x86_pmu.version >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * No need to reprogram LBR_SELECT in a PMI, as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * did not change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (cpuc->lbr_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) wrmsrl(MSR_LBR_SELECT, lbr_select);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) orig_debugctl = debugctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) debugctl |= DEBUGCTLMSR_LBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * may cause superfluous increase/decrease of LBR_TOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (is_lbr_call_stack_bit_set(lbr_select))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) debugctl &= ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (orig_debugctl != debugctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (static_cpu_has(X86_FEATURE_ARCH_LBR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void __intel_pmu_lbr_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u64 debugctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (static_cpu_has(X86_FEATURE_ARCH_LBR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) wrmsrl(MSR_ARCH_LBR_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void intel_pmu_lbr_reset_32(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < x86_pmu.lbr_nr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) wrmsrl(x86_pmu.lbr_from + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void intel_pmu_lbr_reset_64(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) wrmsrl(x86_pmu.lbr_from + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) wrmsrl(x86_pmu.lbr_to + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) wrmsrl(x86_pmu.lbr_info + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void intel_pmu_arch_lbr_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Write to ARCH_LBR_DEPTH MSR, all LBR entries are reset to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void intel_pmu_lbr_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!x86_pmu.lbr_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) x86_pmu.lbr_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cpuc->last_task_ctx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cpuc->last_log_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * TOS = most recently recorded branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static inline u64 intel_pmu_lbr_tos(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u64 tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rdmsrl(x86_pmu.lbr_tos, tos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) LBR_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LBR_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * TSX is not supported they have no consistent behavior:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * - For wrmsr(), bits 61:62 are considered part of the sign extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * - For HW updates (branch captures) bits 61:62 are always OFF and are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * part of the sign extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Therefore, if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 1) LBR has TSX format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 2) CPU has no TSX support enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * ... then any value passed to wrmsr() must be sign extended to 63 bits and any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * value from rdmsr() must be converted to have a 61 bits sign extension,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * ignoring the TSX flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline bool lbr_from_signext_quirk_needed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int lbr_format = x86_pmu.intel_cap.lbr_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) boot_cpu_has(X86_FEATURE_RTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* If quirk is enabled, ensure sign extension is 63 bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) inline u64 lbr_from_signext_quirk_wr(u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (static_branch_unlikely(&lbr_from_quirk_key)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Sign extend into bits 61:62 while preserving bit 63.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Quirk is enabled when TSX is disabled. Therefore TSX bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * in val are always OFF and must be changed to be sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * extension bits. Since bits 59:60 are guaranteed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * part of the sign extension bits, we can just copy them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * to 61:62.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * If quirk is needed, ensure sign extension is 61 bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static u64 lbr_from_signext_quirk_rd(u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (static_branch_unlikely(&lbr_from_quirk_key)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Quirk is on when TSX is not enabled. Therefore TSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * flags must be read as OFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static __always_inline void wrlbr_from(unsigned int idx, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val = lbr_from_signext_quirk_wr(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) wrmsrl(x86_pmu.lbr_from + idx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static __always_inline void wrlbr_to(unsigned int idx, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) wrmsrl(x86_pmu.lbr_to + idx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static __always_inline void wrlbr_info(unsigned int idx, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) wrmsrl(x86_pmu.lbr_info + idx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static __always_inline u64 rdlbr_from(unsigned int idx, struct lbr_entry *lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return lbr->from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rdmsrl(x86_pmu.lbr_from + idx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return lbr_from_signext_quirk_rd(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static __always_inline u64 rdlbr_to(unsigned int idx, struct lbr_entry *lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return lbr->to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rdmsrl(x86_pmu.lbr_to + idx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static __always_inline u64 rdlbr_info(unsigned int idx, struct lbr_entry *lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return lbr->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rdmsrl(x86_pmu.lbr_info + idx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) wrlbr_all(struct lbr_entry *lbr, unsigned int idx, bool need_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) wrlbr_from(idx, lbr->from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) wrlbr_to(idx, lbr->to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (need_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) wrlbr_info(idx, lbr->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rdlbr_all(struct lbr_entry *lbr, unsigned int idx, bool need_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u64 from = rdlbr_from(idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Don't read invalid entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) lbr->from = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) lbr->to = rdlbr_to(idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (need_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) lbr->info = rdlbr_info(idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void intel_pmu_lbr_restore(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct x86_perf_task_context *task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned lbr_idx, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u64 tos = task_ctx->tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mask = x86_pmu.lbr_nr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (i = 0; i < task_ctx->valid_lbrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) lbr_idx = (tos - i) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) wrlbr_all(&task_ctx->lbr[i], lbr_idx, need_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) lbr_idx = (tos - i) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) wrlbr_from(lbr_idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) wrlbr_to(lbr_idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) wrlbr_info(lbr_idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) wrmsrl(x86_pmu.lbr_tos, tos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (cpuc->lbr_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) wrmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void intel_pmu_arch_lbr_restore(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct x86_perf_task_context_arch_lbr *task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct lbr_entry *entries = task_ctx->entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Fast reset the LBRs before restore if the call stack is not full. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!entries[x86_pmu.lbr_nr - 1].from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) intel_pmu_arch_lbr_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for (i = 0; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!entries[i].from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) wrlbr_all(&entries[i], i, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Restore the Architecture LBR state from the xsave area in the perf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * context data for the task via the XRSTORS instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void intel_pmu_arch_lbr_xrstors(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct x86_perf_task_context_arch_lbr_xsave *task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) copy_kernel_to_dynamic_supervisor(&task_ctx->xsave, XFEATURE_MASK_LBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static __always_inline bool lbr_is_reset_in_cstate(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (static_cpu_has(X86_FEATURE_ARCH_LBR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return x86_pmu.lbr_deep_c_reset && !rdlbr_from(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return !rdlbr_from(((struct x86_perf_task_context *)ctx)->tos, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void __intel_pmu_lbr_restore(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (task_context_opt(ctx)->lbr_callstack_users == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) task_context_opt(ctx)->lbr_stack_state == LBR_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) intel_pmu_lbr_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Does not restore the LBR registers, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * - No one else touched them, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * - Was not cleared in Cstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if ((ctx == cpuc->last_task_ctx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (task_context_opt(ctx)->log_id == cpuc->last_log_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) !lbr_is_reset_in_cstate(ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) task_context_opt(ctx)->lbr_stack_state = LBR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) x86_pmu.lbr_restore(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) task_context_opt(ctx)->lbr_stack_state = LBR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void intel_pmu_lbr_save(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) bool need_info = x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct x86_perf_task_context *task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned lbr_idx, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u64 tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mask = x86_pmu.lbr_nr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tos = intel_pmu_lbr_tos();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for (i = 0; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) lbr_idx = (tos - i) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!rdlbr_all(&task_ctx->lbr[i], lbr_idx, need_info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) task_ctx->valid_lbrs = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) task_ctx->tos = tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (cpuc->lbr_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) rdmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void intel_pmu_arch_lbr_save(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct x86_perf_task_context_arch_lbr *task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct lbr_entry *entries = task_ctx->entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!rdlbr_all(&entries[i], i, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* LBR call stack is not full. Reset is required in restore. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (i < x86_pmu.lbr_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) entries[x86_pmu.lbr_nr - 1].from = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Save the Architecture LBR state to the xsave area in the perf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * context data for the task via the XSAVES instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void intel_pmu_arch_lbr_xsaves(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct x86_perf_task_context_arch_lbr_xsave *task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) copy_dynamic_supervisor_to_kernel(&task_ctx->xsave, XFEATURE_MASK_LBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static void __intel_pmu_lbr_save(void *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (task_context_opt(ctx)->lbr_callstack_users == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) task_context_opt(ctx)->lbr_stack_state = LBR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) x86_pmu.lbr_save(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) task_context_opt(ctx)->lbr_stack_state = LBR_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cpuc->last_task_ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cpuc->last_log_id = ++task_context_opt(ctx)->log_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct perf_event_context *next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void *prev_ctx_data, *next_ctx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) swap(prev->task_ctx_data, next->task_ctx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * Architecture specific synchronization makes sense in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * case both prev->task_ctx_data and next->task_ctx_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * pointers are allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) prev_ctx_data = next->task_ctx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) next_ctx_data = prev->task_ctx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!prev_ctx_data || !next_ctx_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) swap(task_context_opt(prev_ctx_data)->lbr_callstack_users,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) task_context_opt(next_ctx_data)->lbr_callstack_users);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void *task_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!cpuc->lbr_users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * If LBR callstack feature is enabled and the stack was saved when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * the task was scheduled out, restore the stack. Otherwise flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * the LBR stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) task_ctx = ctx ? ctx->task_ctx_data : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (task_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (sched_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __intel_pmu_lbr_restore(task_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __intel_pmu_lbr_save(task_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Since a context switch can flip the address space and LBR entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * are not tagged with an identifier, we need to wipe the LBR, even for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * per-cpu events. You simply cannot resolve the branches from the old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (sched_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) intel_pmu_lbr_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static inline bool branch_user_callstack(unsigned br_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void intel_pmu_lbr_add(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!x86_pmu.lbr_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (event->hw.flags & PERF_X86_EVENT_LBR_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) cpuc->lbr_select = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) cpuc->br_sel = event->hw.branch_reg.reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (branch_user_callstack(cpuc->br_sel) && event->ctx->task_ctx_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) task_context_opt(event->ctx->task_ctx_data)->lbr_callstack_users++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * Request pmu::sched_task() callback, which will fire inside the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * regular perf event scheduling, so that call will:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * - restore or wipe; when LBR-callstack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * - wipe; otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * when this is from __perf_event_task_sched_in().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * However, if this is from perf_install_in_context(), no such callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * will follow and we'll need to reset the LBR here if this is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * first LBR event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * The problem is, we cannot tell these cases apart... but we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * exclude the biggest chunk of cases by looking at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * event->total_time_running. An event that has accrued runtime cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * be 'new'. Conversely, a new event can get installed through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * context switch path for the first time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) cpuc->lbr_pebs_users++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) perf_sched_cb_inc(event->ctx->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!cpuc->lbr_users++ && !event->total_time_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) intel_pmu_lbr_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) void release_lbr_buffers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct kmem_cache *kmem_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct cpu_hw_events *cpuc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) kmem_cache = x86_get_pmu(cpu)->task_ctx_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (kmem_cache && cpuc->lbr_xsave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) kmem_cache_free(kmem_cache, cpuc->lbr_xsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cpuc->lbr_xsave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) void reserve_lbr_buffers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct kmem_cache *kmem_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct cpu_hw_events *cpuc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) kmem_cache = x86_get_pmu(cpu)->task_ctx_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!kmem_cache || cpuc->lbr_xsave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cpuc->lbr_xsave = kmem_cache_alloc_node(kmem_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) GFP_KERNEL | __GFP_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cpu_to_node(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) void intel_pmu_lbr_del(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (!x86_pmu.lbr_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (branch_user_callstack(cpuc->br_sel) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) event->ctx->task_ctx_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) task_context_opt(event->ctx->task_ctx_data)->lbr_callstack_users--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (event->hw.flags & PERF_X86_EVENT_LBR_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) cpuc->lbr_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cpuc->lbr_pebs_users--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) cpuc->lbr_users--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) WARN_ON_ONCE(cpuc->lbr_users < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) WARN_ON_ONCE(cpuc->lbr_pebs_users < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) perf_sched_cb_dec(event->ctx->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static inline bool vlbr_exclude_host(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return test_bit(INTEL_PMC_IDX_FIXED_VLBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) (unsigned long *)&cpuc->intel_ctrl_guest_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) void intel_pmu_lbr_enable_all(bool pmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (cpuc->lbr_users && !vlbr_exclude_host())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) __intel_pmu_lbr_enable(pmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void intel_pmu_lbr_disable_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (cpuc->lbr_users && !vlbr_exclude_host())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __intel_pmu_lbr_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned long mask = x86_pmu.lbr_nr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u64 tos = intel_pmu_lbr_tos();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) for (i = 0; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned long lbr_idx = (tos - i) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u64 lbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) } msr_lastbranch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) cpuc->lbr_entries[i].from = msr_lastbranch.from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) cpuc->lbr_entries[i].to = msr_lastbranch.to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) cpuc->lbr_entries[i].mispred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cpuc->lbr_entries[i].predicted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) cpuc->lbr_entries[i].in_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cpuc->lbr_entries[i].abort = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cpuc->lbr_entries[i].cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cpuc->lbr_entries[i].type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) cpuc->lbr_entries[i].reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) cpuc->lbr_stack.nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) cpuc->lbr_stack.hw_idx = tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * Due to lack of segmentation in Linux the effective address (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * is the same as the linear address, allowing us to merge the LIP and EIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * LBR formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) bool need_info = false, call_stack = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned long mask = x86_pmu.lbr_nr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int lbr_format = x86_pmu.intel_cap.lbr_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u64 tos = intel_pmu_lbr_tos();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int out = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int num = x86_pmu.lbr_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (cpuc->lbr_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (cpuc->lbr_sel->config & LBR_CALL_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) call_stack = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned long lbr_idx = (tos - i) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int skip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u16 cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int lbr_flags = lbr_desc[lbr_format];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) from = rdlbr_from(lbr_idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) to = rdlbr_to(lbr_idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * Read LBR call stack entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * until invalid entry (0s) is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (call_stack && !from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (lbr_format == LBR_FORMAT_INFO && need_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u64 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) info = rdlbr_info(lbr_idx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mis = !!(info & LBR_INFO_MISPRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pred = !mis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) in_tx = !!(info & LBR_INFO_IN_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) abort = !!(info & LBR_INFO_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) cycles = (info & LBR_INFO_CYCLES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (lbr_format == LBR_FORMAT_TIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mis = !!(from & LBR_FROM_FLAG_MISPRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pred = !mis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) skip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) cycles = ((to >> 48) & LBR_INFO_CYCLES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) to = (u64)((((s64)to) << 16) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (lbr_flags & LBR_EIP_FLAGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mis = !!(from & LBR_FROM_FLAG_MISPRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pred = !mis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) skip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (lbr_flags & LBR_TSX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) abort = !!(from & LBR_FROM_FLAG_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) skip = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) from = (u64)((((s64)from) << skip) >> skip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * Some CPUs report duplicated abort records,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * with the second entry not having an abort bit set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * Skip them here. This loop runs backwards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * so we need to undo the previous record.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * If the abort just happened outside the window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * the extra entry cannot be removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (abort && x86_pmu.lbr_double_abort && out > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) out--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) cpuc->lbr_entries[out].from = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) cpuc->lbr_entries[out].to = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) cpuc->lbr_entries[out].mispred = mis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) cpuc->lbr_entries[out].predicted = pred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) cpuc->lbr_entries[out].in_tx = in_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cpuc->lbr_entries[out].abort = abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) cpuc->lbr_entries[out].cycles = cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) cpuc->lbr_entries[out].type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) cpuc->lbr_entries[out].reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) out++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) cpuc->lbr_stack.nr = out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) cpuc->lbr_stack.hw_idx = tos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static __always_inline int get_lbr_br_type(u64 info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!static_cpu_has(X86_FEATURE_ARCH_LBR) || !x86_pmu.lbr_br_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return (info & LBR_INFO_BR_TYPE) >> LBR_INFO_BR_TYPE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static __always_inline bool get_lbr_mispred(u64 info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return !!(info & LBR_INFO_MISPRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static __always_inline bool get_lbr_predicted(u64 info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (static_cpu_has(X86_FEATURE_ARCH_LBR) && !x86_pmu.lbr_mispred)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return !(info & LBR_INFO_MISPRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static __always_inline u16 get_lbr_cycles(u64 info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) !(x86_pmu.lbr_timed_lbr && info & LBR_INFO_CYC_CNT_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return info & LBR_INFO_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct lbr_entry *entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct perf_branch_entry *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct lbr_entry *lbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u64 from, to, info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) for (i = 0; i < x86_pmu.lbr_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) lbr = entries ? &entries[i] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) e = &cpuc->lbr_entries[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) from = rdlbr_from(i, lbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * Read LBR entries until invalid entry (0s) is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (!from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) to = rdlbr_to(i, lbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) info = rdlbr_info(i, lbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) e->from = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) e->to = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) e->mispred = get_lbr_mispred(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) e->predicted = get_lbr_predicted(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) e->in_tx = !!(info & LBR_INFO_IN_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) e->abort = !!(info & LBR_INFO_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) e->cycles = get_lbr_cycles(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) e->type = get_lbr_br_type(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) e->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) cpuc->lbr_stack.nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static void intel_pmu_arch_lbr_read(struct cpu_hw_events *cpuc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) intel_pmu_store_lbr(cpuc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void intel_pmu_arch_lbr_read_xsave(struct cpu_hw_events *cpuc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct x86_perf_task_context_arch_lbr_xsave *xsave = cpuc->lbr_xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!xsave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) intel_pmu_store_lbr(cpuc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) copy_dynamic_supervisor_to_kernel(&xsave->xsave, XFEATURE_MASK_LBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) intel_pmu_store_lbr(cpuc, xsave->lbr.entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) void intel_pmu_lbr_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * Don't read when all LBRs users are using adaptive PEBS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * This could be smarter and actually check the event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * but this simple approach seems to work for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!cpuc->lbr_users || vlbr_exclude_host() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) cpuc->lbr_users == cpuc->lbr_pebs_users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) x86_pmu.lbr_read(cpuc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) intel_pmu_lbr_filter(cpuc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * SW filter is used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * - in case there is no HW filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * - in case the HW filter has errata or limitations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) u64 br_type = event->attr.branch_sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (br_type & PERF_SAMPLE_BRANCH_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mask |= X86_BR_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mask |= X86_BR_KERNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* we ignore BRANCH_HV here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (br_type & PERF_SAMPLE_BRANCH_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) mask |= X86_BR_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mask |= X86_BR_ANY_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mask |= X86_BR_IND_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mask |= X86_BR_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mask |= X86_BR_IN_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mask |= X86_BR_NO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (br_type & PERF_SAMPLE_BRANCH_COND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) mask |= X86_BR_JCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!x86_pmu_has_lbr_callstack())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (mask & ~(X86_BR_USER | X86_BR_KERNEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) X86_BR_CALL_STACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mask |= X86_BR_IND_JMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (br_type & PERF_SAMPLE_BRANCH_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mask |= X86_BR_TYPE_SAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * stash actual user request into reg, it may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * be used by fixup code for some CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) event->hw.branch_reg.reg = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * setup the HW LBR filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * Used only when available, may not be enough to disambiguate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * all branches, may need the help of the SW filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct hw_perf_event_extra *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u64 br_type = event->attr.branch_sample_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u64 mask = 0, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!(br_type & (1ULL << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) v = x86_pmu.lbr_sel_map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (v == LBR_NOT_SUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (v != LBR_IGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mask |= v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) reg = &event->hw.branch_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) reg->idx = EXTRA_REG_LBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (static_cpu_has(X86_FEATURE_ARCH_LBR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) reg->config = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * in suppress mode. So LBR_SELECT should be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * But the 10th bit LBR_CALL_STACK does not operate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * in suppress mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) reg->config |= LBR_NO_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int intel_pmu_setup_lbr_filter(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * no LBR on this PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!x86_pmu.lbr_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * setup SW LBR filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ret = intel_pmu_setup_sw_lbr_filter(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * setup HW LBR filter, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (x86_pmu.lbr_sel_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret = intel_pmu_setup_hw_lbr_filter(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * return the type of control flow change at address "from"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * instruction is not necessarily a branch (in case of interrupt).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * The branch type returned also includes the priv level of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * If a branch type is unknown OR the instruction cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * decoded (e.g., text page not present), then X86_BR_NONE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int branch_type(unsigned long from, unsigned long to, int abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct insn insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int bytes_read, bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int ret = X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int ext, to_plm, from_plm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u8 buf[MAX_INSN_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int is64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * maybe zero if lbr did not fill up after a reset by the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * we get a PMU interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (from == 0 || to == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return X86_BR_ABORT | to_plm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (from_plm == X86_BR_USER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * can happen if measuring at the user level only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * and we interrupt in a kernel thread, e.g., idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!current->mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* may fail if text not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) bytes_left = copy_from_user_nmi(buf, (void __user *)from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) MAX_INSN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bytes_read = MAX_INSN_SIZE - bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (!bytes_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) addr = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * The LBR logs any address in the IP, even if the IP just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * faulted. This means userspace can control the from address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Ensure we don't blindy read any address by validating it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * a known text address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (kernel_text_address(from)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) addr = (void *)from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * Assume we can get the maximum possible size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * when grabbing kernel data. This is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * _strictly_ true since we could possibly be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * executing up next to a memory hole, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * it is very unlikely to be a problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) bytes_read = MAX_INSN_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * decoder needs to know the ABI especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * on 64-bit systems running 32-bit apps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) insn_init(&insn, addr, bytes_read, is64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) insn_get_opcode(&insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!insn.opcode.got)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return X86_BR_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) switch (insn.opcode.bytes[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) case 0xf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) switch (insn.opcode.bytes[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case 0x05: /* syscall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case 0x34: /* sysenter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = X86_BR_SYSCALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case 0x07: /* sysret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) case 0x35: /* sysexit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ret = X86_BR_SYSRET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) case 0x80 ... 0x8f: /* conditional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = X86_BR_JCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case 0x70 ... 0x7f: /* conditional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = X86_BR_JCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case 0xc2: /* near ret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case 0xc3: /* near ret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) case 0xca: /* far ret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case 0xcb: /* far ret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = X86_BR_RET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case 0xcf: /* iret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret = X86_BR_IRET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case 0xcc ... 0xce: /* int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = X86_BR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case 0xe8: /* call near rel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) insn_get_immediate(&insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (insn.immediate1.value == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* zero length call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = X86_BR_ZERO_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case 0x9a: /* call far absolute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = X86_BR_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) case 0xe0 ... 0xe3: /* loop jmp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = X86_BR_JCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) case 0xe9 ... 0xeb: /* jmp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ret = X86_BR_JMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case 0xff: /* call near absolute, call far absolute ind */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) insn_get_modrm(&insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ext = (insn.modrm.bytes[0] >> 3) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) switch (ext) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case 2: /* near ind call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) case 3: /* far ind call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = X86_BR_IND_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = X86_BR_IND_JMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = X86_BR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * interrupts, traps, faults (and thus ring transition) may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * occur on any instructions. Thus, to classify them correctly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * we need to first look at the from and to priv levels. If they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * are different and to is in the kernel, then it indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * a ring transition. If the from instruction is not a ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * transition instr (syscall, systenter, int), then it means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * it was a irq, trap or fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * we have no way of detecting kernel to kernel faults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ret = X86_BR_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * branch priv level determined by target as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * is done by HW when LBR_SELECT is implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret != X86_BR_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ret |= to_plm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define X86_BR_TYPE_MAP_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static int branch_map[X86_BR_TYPE_MAP_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PERF_BR_CALL, /* X86_BR_CALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PERF_BR_RET, /* X86_BR_RET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PERF_BR_SYSRET, /* X86_BR_SYSRET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PERF_BR_UNKNOWN, /* X86_BR_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PERF_BR_UNKNOWN, /* X86_BR_IRET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PERF_BR_COND, /* X86_BR_JCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PERF_BR_UNCOND, /* X86_BR_JMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PERF_BR_UNKNOWN, /* X86_BR_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PERF_BR_UNKNOWN, /* X86_BR_ABORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PERF_BR_UNKNOWN, /* X86_BR_NO_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PERF_BR_CALL, /* X86_BR_ZERO_CALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PERF_BR_IND, /* X86_BR_IND_JMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) common_branch_type(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) i = __ffs(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (i < X86_BR_TYPE_MAP_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return branch_map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return PERF_BR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ARCH_LBR_BR_TYPE_JCC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ARCH_LBR_BR_TYPE_NEAR_IND_JMP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ARCH_LBR_BR_TYPE_NEAR_REL_JMP = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ARCH_LBR_BR_TYPE_NEAR_IND_CALL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ARCH_LBR_BR_TYPE_NEAR_REL_CALL = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ARCH_LBR_BR_TYPE_NEAR_RET = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ARCH_LBR_BR_TYPE_KNOWN_MAX = ARCH_LBR_BR_TYPE_NEAR_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ARCH_LBR_BR_TYPE_MAP_MAX = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static const int arch_lbr_br_type_map[ARCH_LBR_BR_TYPE_MAP_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) [ARCH_LBR_BR_TYPE_JCC] = X86_BR_JCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) [ARCH_LBR_BR_TYPE_NEAR_IND_JMP] = X86_BR_IND_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) [ARCH_LBR_BR_TYPE_NEAR_REL_JMP] = X86_BR_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) [ARCH_LBR_BR_TYPE_NEAR_IND_CALL] = X86_BR_IND_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) [ARCH_LBR_BR_TYPE_NEAR_REL_CALL] = X86_BR_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) [ARCH_LBR_BR_TYPE_NEAR_RET] = X86_BR_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * implement actual branch filter based on user demand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * Hardware may not exactly satisfy that request, thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * we need to inspect opcodes. Mismatched branches are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * discarded. Therefore, the number of branches returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * in PERF_SAMPLE_BRANCH_STACK sample may vary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) u64 from, to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int br_sel = cpuc->br_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) int i, j, type, to_plm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) bool compress = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* if sampling all branches, then nothing to filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (((br_sel & X86_BR_ALL) == X86_BR_ALL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) for (i = 0; i < cpuc->lbr_stack.nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) from = cpuc->lbr_entries[i].from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) to = cpuc->lbr_entries[i].to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) type = cpuc->lbr_entries[i].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * Parse the branch type recorded in LBR_x_INFO MSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * Doesn't support OTHER_BRANCH decoding for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * OTHER_BRANCH branch type still rely on software decoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) type <= ARCH_LBR_BR_TYPE_KNOWN_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) type = arch_lbr_br_type_map[type] | to_plm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) type = branch_type(from, to, cpuc->lbr_entries[i].abort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (cpuc->lbr_entries[i].in_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) type |= X86_BR_IN_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) type |= X86_BR_NO_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* if type does not correspond, then discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (type == X86_BR_NONE || (br_sel & type) != type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) cpuc->lbr_entries[i].from = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) compress = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) cpuc->lbr_entries[i].type = common_branch_type(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!compress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* remove all entries with from=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) for (i = 0; i < cpuc->lbr_stack.nr; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (!cpuc->lbr_entries[i].from) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) j = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) while (++j < cpuc->lbr_stack.nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) cpuc->lbr_stack.nr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (!cpuc->lbr_entries[i].from)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* Cannot get TOS for large PEBS and Arch LBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (static_cpu_has(X86_FEATURE_ARCH_LBR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) (cpuc->n_pebs == cpuc->n_large_pebs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) cpuc->lbr_stack.hw_idx = -1ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) cpuc->lbr_stack.hw_idx = intel_pmu_lbr_tos();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) intel_pmu_store_lbr(cpuc, lbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) intel_pmu_lbr_filter(cpuc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * Map interface branch filters onto LBR filters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) | LBR_IND_JMP | LBR_FAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) | LBR_FAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) | LBR_FAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) | LBR_RETURN | LBR_CALL_STACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static int arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) [PERF_SAMPLE_BRANCH_ANY_SHIFT] = ARCH_LBR_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) [PERF_SAMPLE_BRANCH_USER_SHIFT] = ARCH_LBR_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = ARCH_LBR_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = ARCH_LBR_RETURN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ARCH_LBR_OTHER_BRANCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = ARCH_LBR_REL_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ARCH_LBR_IND_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ARCH_LBR_OTHER_BRANCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = ARCH_LBR_IND_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) [PERF_SAMPLE_BRANCH_COND_SHIFT] = ARCH_LBR_JCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = ARCH_LBR_REL_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ARCH_LBR_IND_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ARCH_LBR_RETURN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ARCH_LBR_CALL_STACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = ARCH_LBR_IND_JMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) [PERF_SAMPLE_BRANCH_CALL_SHIFT] = ARCH_LBR_REL_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) void __init intel_pmu_lbr_init_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) x86_pmu.lbr_nr = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) x86_pmu.lbr_to = MSR_LBR_CORE_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * SW branch filter usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * - compensate for lack of HW filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* nehalem/westmere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) void __init intel_pmu_lbr_init_nhm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) x86_pmu.lbr_nr = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) x86_pmu.lbr_to = MSR_LBR_NHM_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * SW branch filter usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * - workaround LBR_SEL errata (see above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * - support syscall, sysret capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * That requires LBR_FAR but that means far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * jmp need to be filtered out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* sandy bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) void __init intel_pmu_lbr_init_snb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) x86_pmu.lbr_nr = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) x86_pmu.lbr_to = MSR_LBR_NHM_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) x86_pmu.lbr_sel_map = snb_lbr_sel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * SW branch filter usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * - support syscall, sysret capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * That requires LBR_FAR but that means far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * jmp need to be filtered out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static inline struct kmem_cache *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) create_lbr_kmem_cache(size_t size, size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return kmem_cache_create("x86_lbr", size, align, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* haswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) void intel_pmu_lbr_init_hsw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) size_t size = sizeof(struct x86_perf_task_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) x86_pmu.lbr_nr = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) x86_pmu.lbr_to = MSR_LBR_NHM_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (lbr_from_signext_quirk_needed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static_branch_enable(&lbr_from_quirk_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* skylake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) __init void intel_pmu_lbr_init_skl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) size_t size = sizeof(struct x86_perf_task_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) x86_pmu.lbr_nr = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) x86_pmu.lbr_to = MSR_LBR_NHM_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) x86_pmu.lbr_info = MSR_LBR_INFO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) x86_get_pmu(smp_processor_id())->task_ctx_cache = create_lbr_kmem_cache(size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * SW branch filter usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * - support syscall, sysret capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * That requires LBR_FAR but that means far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * jmp need to be filtered out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* atom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) void __init intel_pmu_lbr_init_atom(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * only models starting at stepping 10 seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * to have an operational LBR which can freeze
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * on PMU interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (boot_cpu_data.x86_model == 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) && boot_cpu_data.x86_stepping < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pr_cont("LBR disabled due to erratum");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) x86_pmu.lbr_nr = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) x86_pmu.lbr_to = MSR_LBR_CORE_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * SW branch filter usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * - compensate for lack of HW filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* slm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) void __init intel_pmu_lbr_init_slm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) x86_pmu.lbr_nr = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) x86_pmu.lbr_to = MSR_LBR_CORE_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * SW branch filter usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * - compensate for lack of HW filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) pr_cont("8-deep LBR, ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* Knights Landing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) void intel_pmu_lbr_init_knl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) x86_pmu.lbr_nr = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) x86_pmu.lbr_tos = MSR_LBR_TOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) x86_pmu.lbr_to = MSR_LBR_NHM_TO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) x86_pmu.lbr_sel_map = snb_lbr_sel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Knights Landing does have MISPREDICT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * LBR state size is variable based on the max number of registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * This calculates the expected state size, which should match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * what the hardware enumerates for the size of XFEATURE_LBR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static inline unsigned int get_lbr_state_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return sizeof(struct arch_lbr_state) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) x86_pmu.lbr_nr * sizeof(struct lbr_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static bool is_arch_lbr_xsave_available(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (!boot_cpu_has(X86_FEATURE_XSAVES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * Check the LBR state with the corresponding software structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * Disable LBR XSAVES support if the size doesn't match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (xfeature_size(XFEATURE_LBR) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (WARN_ON(xfeature_size(XFEATURE_LBR) != get_lbr_state_size()))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) void __init intel_pmu_arch_lbr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct pmu *pmu = x86_get_pmu(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) union cpuid28_eax eax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) union cpuid28_ebx ebx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) union cpuid28_ecx ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) unsigned int unused_edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) bool arch_lbr_xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) u64 lbr_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* Arch LBR Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) cpuid(28, &eax.full, &ebx.full, &ecx.full, &unused_edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) lbr_nr = fls(eax.split.lbr_depth_mask) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (!lbr_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) goto clear_arch_lbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* Apply the max depth of Arch LBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (wrmsrl_safe(MSR_ARCH_LBR_DEPTH, lbr_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) goto clear_arch_lbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) x86_pmu.lbr_deep_c_reset = eax.split.lbr_deep_c_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) x86_pmu.lbr_lip = eax.split.lbr_lip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) x86_pmu.lbr_cpl = ebx.split.lbr_cpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) x86_pmu.lbr_filter = ebx.split.lbr_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) x86_pmu.lbr_call_stack = ebx.split.lbr_call_stack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) x86_pmu.lbr_mispred = ecx.split.lbr_mispred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) x86_pmu.lbr_br_type = ecx.split.lbr_br_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) x86_pmu.lbr_nr = lbr_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) arch_lbr_xsave = is_arch_lbr_xsave_available();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (arch_lbr_xsave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) size = sizeof(struct x86_perf_task_context_arch_lbr_xsave) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) get_lbr_state_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) pmu->task_ctx_cache = create_lbr_kmem_cache(size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) XSAVE_ALIGNMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (!pmu->task_ctx_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) arch_lbr_xsave = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) size = sizeof(struct x86_perf_task_context_arch_lbr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) lbr_nr * sizeof(struct lbr_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) pmu->task_ctx_cache = create_lbr_kmem_cache(size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) x86_pmu.lbr_from = MSR_ARCH_LBR_FROM_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) x86_pmu.lbr_to = MSR_ARCH_LBR_TO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) x86_pmu.lbr_info = MSR_ARCH_LBR_INFO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* LBR callstack requires both CPL and Branch Filtering support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (!x86_pmu.lbr_cpl ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) !x86_pmu.lbr_filter ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) !x86_pmu.lbr_call_stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!x86_pmu.lbr_cpl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) } else if (!x86_pmu.lbr_filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) arch_lbr_ctl_map[PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_NOT_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) x86_pmu.lbr_ctl_mask = ARCH_LBR_CTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) x86_pmu.lbr_ctl_map = arch_lbr_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (!x86_pmu.lbr_cpl && !x86_pmu.lbr_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) x86_pmu.lbr_ctl_map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) x86_pmu.lbr_reset = intel_pmu_arch_lbr_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (arch_lbr_xsave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) x86_pmu.lbr_save = intel_pmu_arch_lbr_xsaves;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) x86_pmu.lbr_restore = intel_pmu_arch_lbr_xrstors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) x86_pmu.lbr_read = intel_pmu_arch_lbr_read_xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) pr_cont("XSAVE ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) x86_pmu.lbr_save = intel_pmu_arch_lbr_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) x86_pmu.lbr_restore = intel_pmu_arch_lbr_restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) x86_pmu.lbr_read = intel_pmu_arch_lbr_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) pr_cont("Architectural LBR, ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) clear_arch_lbr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) clear_cpu_cap(&boot_cpu_data, X86_FEATURE_ARCH_LBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * x86_perf_get_lbr - get the LBR records information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * @lbr: the caller's memory to store the LBR records information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * Returns: 0 indicates the LBR info has been successfully obtained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int lbr_fmt = x86_pmu.intel_cap.lbr_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) lbr->nr = x86_pmu.lbr_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) lbr->from = x86_pmu.lbr_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) lbr->to = x86_pmu.lbr_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) EXPORT_SYMBOL_GPL(x86_perf_get_lbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct event_constraint vlbr_constraint =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) __EVENT_CONSTRAINT(INTEL_FIXED_VLBR_EVENT, (1ULL << INTEL_PMC_IDX_FIXED_VLBR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) FIXED_EVENT_FLAGS, 1, 0, PERF_X86_EVENT_LBR_SELECT);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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