^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance events - AMD Processor Power Reporting Mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Huang Rui <ray.huang@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "../perf_event.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AMD_POWER_EVENT_MASK 0xFFULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Accumulated power status counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AMD_POWER_EVENTSEL_PKG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The ratio of compute unit power accumulator sample period to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * PTSC period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static unsigned int cpu_pwr_sample_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Maximum accumulated power of a compute unit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static u64 max_cu_acc_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct pmu pmu_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Accumulated power represents the sum of each compute unit's (CU) power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * consumption. On any core of each CU we read the total accumulated power from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * MSR_F15H_CU_PWR_ACCUMULATOR. cpu_mask represents CPU bit map of all cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * which are picked to measure the power for the CUs they belong to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static cpumask_t cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void event_update(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u64 prev_pwr_acc, new_pwr_acc, prev_ptsc, new_ptsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 delta, tdelta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) prev_pwr_acc = hwc->pwr_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) prev_ptsc = hwc->ptsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) rdmsrl(MSR_F15H_PTSC, new_ptsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Calculate the CU power consumption over a time period, the unit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * final value (delta) is micro-Watts. Then add it to the event count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (new_pwr_acc < prev_pwr_acc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) delta = max_cu_acc_power + new_pwr_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) delta -= prev_pwr_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) delta = new_pwr_acc - prev_pwr_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) delta *= cpu_pwr_sample_ratio * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tdelta = new_ptsc - prev_ptsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) do_div(delta, tdelta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void __pmu_event_start(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) event->hw.state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rdmsrl(MSR_F15H_PTSC, event->hw.ptsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void pmu_event_start(struct perf_event *event, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __pmu_event_start(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void pmu_event_stop(struct perf_event *event, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Mark event as deactivated and stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!(hwc->state & PERF_HES_STOPPED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) hwc->state |= PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Check if software counter update is necessary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Drain the remaining delta count out of an event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * that we are disabling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hwc->state |= PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int pmu_event_add(struct perf_event *event, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (mode & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __pmu_event_start(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void pmu_event_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pmu_event_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int pmu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u64 cfg = event->attr.config & AMD_POWER_EVENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Only look at AMD power events. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (event->attr.type != pmu_class.type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Unsupported modes and filters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (event->attr.sample_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (cfg != AMD_POWER_EVENTSEL_PKG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void pmu_event_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) event_update(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) get_attr_cpumask(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return cpumap_print_to_pagebuf(true, buf, &cpu_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static DEVICE_ATTR(cpumask, S_IRUGO, get_attr_cpumask, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct attribute *pmu_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &dev_attr_cpumask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct attribute_group pmu_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .attrs = pmu_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Currently it only supports to report the power of each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * processor/package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EVENT_ATTR_STR(power-pkg, power_pkg, "event=0x01");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EVENT_ATTR_STR(power-pkg.unit, power_pkg_unit, "mWatts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Convert the count from micro-Watts to milli-Watts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EVENT_ATTR_STR(power-pkg.scale, power_pkg_scale, "1.000000e-3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct attribute *events_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EVENT_PTR(power_pkg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) EVENT_PTR(power_pkg_unit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EVENT_PTR(power_pkg_scale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct attribute_group pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .attrs = events_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PMU_FORMAT_ATTR(event, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct attribute *formats_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct attribute_group pmu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .attrs = formats_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct attribute_group *attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) &pmu_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) &pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct pmu pmu_class = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .attr_groups = attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* system-wide only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .event_init = pmu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .add = pmu_event_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .del = pmu_event_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .start = pmu_event_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .stop = pmu_event_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .read = pmu_event_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int power_cpu_exit(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!cpumask_test_and_clear_cpu(cpu, &cpu_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Find a new CPU on the same compute unit, if was set in cpumask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * and still some CPUs on compute unit. Then migrate event and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * context to new CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (target < nr_cpumask_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cpumask_set_cpu(target, &cpu_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) perf_pmu_migrate_context(&pmu_class, cpu, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int power_cpu_init(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * 1) If any CPU is set at cpu_mask in the same compute unit, do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * 2) If no CPU is set at cpu_mask in the same compute unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * set current ONLINE CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Note: if there is a CPU aside of the new one already in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * sibling mask, then it is also in cpu_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (target >= nr_cpumask_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cpumask_set_cpu(cpu, &cpu_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct x86_cpu_id cpu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) X86_MATCH_VENDOR_FAM(AMD, 0x15, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __init amd_power_pmu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!x86_match_cpu(cpu_match))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_err("Failed to read max compute unit power accumulator MSR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "perf/x86/amd/power:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) power_cpu_init, power_cpu_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = perf_pmu_register(&pmu_class, "power", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (WARN_ON(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pr_warn("AMD Power PMU registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pr_info("AMD Power PMU detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) module_init(amd_power_pmu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void __exit amd_power_pmu_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_AMD_POWER_ONLINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) perf_pmu_unregister(&pmu_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) module_exit(amd_power_pmu_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DESCRIPTION("AMD Processor Power Reporting Mechanism");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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