Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2013 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Steven Kinney <Steven.Kinney@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _PERF_EVENT_AMD_IOMMU_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _PERF_EVENT_AMD_IOMMU_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* iommu pc mmio region register indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IOMMU_PC_COUNTER_REG			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IOMMU_PC_COUNTER_SRC_REG		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IOMMU_PC_PASID_MATCH_REG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IOMMU_PC_DOMID_MATCH_REG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IOMMU_PC_DEVID_MATCH_REG		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IOMMU_PC_COUNTER_REPORT_REG		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* maximun specified bank/counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PC_MAX_SPEC_BNKS			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PC_MAX_SPEC_CNTRS			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct amd_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* amd_iommu_init.c external support functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern int amd_iommu_get_num_iommus(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern bool amd_iommu_pc_supported(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 				u8 fxn, u64 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				u8 fxn, u64 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern struct amd_iommu *get_amd_iommu(int idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif /*_PERF_EVENT_AMD_IOMMU_H_*/