^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Steven Kinney <Steven.Kinney@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Perf: amd_iommu - AMD IOMMU Performance Counter PMU implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) "perf/amd_iommu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../perf_event.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "iommu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* iommu pmu conf masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GET_CSOURCE(x) ((x)->conf & 0xFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GET_DEVID(x) (((x)->conf >> 8) & 0xFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GET_DOMID(x) (((x)->conf >> 24) & 0xFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GET_PASID(x) (((x)->conf >> 40) & 0xFFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* iommu pmu conf1 masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GET_DEVID_MASK(x) ((x)->conf1 & 0xFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GET_DOMID_MASK(x) (((x)->conf1 >> 16) & 0xFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GET_PASID_MASK(x) (((x)->conf1 >> 32) & 0xFFFFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IOMMU_NAME_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct perf_amd_iommu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct amd_iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) char name[IOMMU_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 max_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 max_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u64 cntr_assign_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static LIST_HEAD(perf_amd_iommu_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * sysfs format attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *---------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PMU_FORMAT_ATTR(csource, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PMU_FORMAT_ATTR(devid, "config:8-23");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PMU_FORMAT_ATTR(domid, "config:24-39");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PMU_FORMAT_ATTR(pasid, "config:40-59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PMU_FORMAT_ATTR(devid_mask, "config1:0-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PMU_FORMAT_ATTR(domid_mask, "config1:16-31");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PMU_FORMAT_ATTR(pasid_mask, "config1:32-51");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct attribute *iommu_format_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) &format_attr_csource.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) &format_attr_devid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) &format_attr_pasid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) &format_attr_domid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) &format_attr_devid_mask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) &format_attr_pasid_mask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) &format_attr_domid_mask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct attribute_group amd_iommu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .attrs = iommu_format_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * sysfs events attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *---------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct attribute_group amd_iommu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct amd_iommu_event_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device_attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const char *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static ssize_t _iommu_event_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct amd_iommu_event_desc *event =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) container_of(attr, struct amd_iommu_event_desc, attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return sprintf(buf, "%s\n", event->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AMD_IOMMU_EVENT_DESC(_name, _event) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .attr = __ATTR(_name, 0444, _iommu_event_show, NULL), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .event = _event, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AMD_IOMMU_EVENT_DESC(mem_pass_untrans, "csource=0x01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AMD_IOMMU_EVENT_DESC(mem_pass_pretrans, "csource=0x02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AMD_IOMMU_EVENT_DESC(mem_pass_excl, "csource=0x03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AMD_IOMMU_EVENT_DESC(mem_target_abort, "csource=0x04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AMD_IOMMU_EVENT_DESC(mem_trans_total, "csource=0x05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_hit, "csource=0x06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_mis, "csource=0x07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_hit, "csource=0x08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_mis, "csource=0x09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AMD_IOMMU_EVENT_DESC(mem_dte_hit, "csource=0x0a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AMD_IOMMU_EVENT_DESC(mem_dte_mis, "csource=0x0b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) AMD_IOMMU_EVENT_DESC(page_tbl_read_tot, "csource=0x0c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) AMD_IOMMU_EVENT_DESC(page_tbl_read_nst, "csource=0x0d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) AMD_IOMMU_EVENT_DESC(page_tbl_read_gst, "csource=0x0e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) AMD_IOMMU_EVENT_DESC(int_dte_hit, "csource=0x0f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AMD_IOMMU_EVENT_DESC(int_dte_mis, "csource=0x10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AMD_IOMMU_EVENT_DESC(cmd_processed, "csource=0x11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) AMD_IOMMU_EVENT_DESC(cmd_processed_inv, "csource=0x12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AMD_IOMMU_EVENT_DESC(tlb_inv, "csource=0x13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) AMD_IOMMU_EVENT_DESC(ign_rd_wr_mmio_1ff8h, "csource=0x14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AMD_IOMMU_EVENT_DESC(vapic_int_non_guest, "csource=0x15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AMD_IOMMU_EVENT_DESC(vapic_int_guest, "csource=0x16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AMD_IOMMU_EVENT_DESC(smi_recv, "csource=0x17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AMD_IOMMU_EVENT_DESC(smi_blk, "csource=0x18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { /* end: all zeroes */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * sysfs cpumask attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *---------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static cpumask_t iommu_cpumask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static ssize_t _iommu_cpumask_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return cpumap_print_to_pagebuf(true, buf, &iommu_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static DEVICE_ATTR(cpumask, S_IRUGO, _iommu_cpumask_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct attribute *iommu_cpumask_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &dev_attr_cpumask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct attribute_group amd_iommu_cpumask_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .attrs = iommu_cpumask_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*---------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int get_next_avail_iommu_bnk_cntr(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct perf_amd_iommu *piommu = container_of(event->pmu, struct perf_amd_iommu, pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int max_cntrs = piommu->max_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int max_banks = piommu->max_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 shift, bank, cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) raw_spin_lock_irqsave(&piommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (bank = 0, shift = 0; bank < max_banks; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) for (cntr = 0; cntr < max_cntrs; cntr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) shift = bank + (bank*3) + cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (piommu->cntr_assign_mask & BIT_ULL(shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) piommu->cntr_assign_mask |= BIT_ULL(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) event->hw.iommu_bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) event->hw.iommu_cntr = cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) retval = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_unlock_irqrestore(&piommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int clear_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 bank, u8 cntr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int max_banks, max_cntrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) max_banks = perf_iommu->max_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) max_cntrs = perf_iommu->max_counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if ((bank > max_banks) || (cntr > max_cntrs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) shift = bank + cntr + (bank*3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) raw_spin_lock_irqsave(&perf_iommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) perf_iommu->cntr_assign_mask &= ~(1ULL<<shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) raw_spin_unlock_irqrestore(&perf_iommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int perf_iommu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* test the event attr type check for PMU enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (event->attr.type != event->pmu->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * IOMMU counters are shared across all cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Therefore, it does not support per-process mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Also, it does not support event sampling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (event->cpu < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* update the hw_perf_event struct with the iommu config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hwc->conf = event->attr.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) hwc->conf1 = event->attr.config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline struct amd_iommu *perf_event_2_iommu(struct perf_event *ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return (container_of(ev->pmu, struct perf_amd_iommu, pmu))->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void perf_iommu_enable_event(struct perf_event *ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct amd_iommu *iommu = perf_event_2_iommu(ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct hw_perf_event *hwc = &ev->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 bank = hwc->iommu_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 cntr = hwc->iommu_cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u64 reg = 0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg = GET_CSOURCE(hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg = GET_DEVID_MASK(hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) reg = GET_DEVID(hwc) | (reg << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reg |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) reg = GET_PASID_MASK(hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg = GET_PASID(hwc) | (reg << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg = GET_DOMID_MASK(hwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg = GET_DOMID(hwc) | (reg << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void perf_iommu_disable_event(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct amd_iommu *iommu = perf_event_2_iommu(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 reg = 0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IOMMU_PC_COUNTER_SRC_REG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void perf_iommu_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) hwc->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * To account for power-gating, which prevents write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * the counter, we need to enable the counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * before setting up counter register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) perf_iommu_enable_event(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (flags & PERF_EF_RELOAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u64 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct amd_iommu *iommu = perf_event_2_iommu(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Since the IOMMU PMU only support counting mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * the counter always start with value zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IOMMU_PC_COUNTER_REG, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void perf_iommu_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u64 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct amd_iommu *iommu = perf_event_2_iommu(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (amd_iommu_pc_get_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) IOMMU_PC_COUNTER_REG, &count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* IOMMU pc counter register is only 48 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) count &= GENMASK_ULL(47, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Since the counter always start with value zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * simply just accumulate the count for the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) local64_add(count, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void perf_iommu_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (hwc->state & PERF_HES_UPTODATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * To account for power-gating, in which reading the counter would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * return zero, we need to read the register before disabling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) perf_iommu_read(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hwc->state |= PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) perf_iommu_disable_event(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) hwc->state |= PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int perf_iommu_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* request an iommu bank/counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) retval = get_next_avail_iommu_bnk_cntr(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) perf_iommu_start(event, PERF_EF_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void perf_iommu_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct perf_amd_iommu *perf_iommu =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) container_of(event->pmu, struct perf_amd_iommu, pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) perf_iommu_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* clear the assigned iommu bank/counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clear_avail_iommu_bnk_cntr(perf_iommu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) hwc->iommu_bank, hwc->iommu_cntr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static __init int _init_events_attrs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int i = 0, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct attribute **attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) while (amd_iommu_v2_event_descs[i].attr.attr.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) attrs = kcalloc(i + 1, sizeof(*attrs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (j = 0; j < i; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) attrs[j] = &amd_iommu_v2_event_descs[j].attr.attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) amd_iommu_events_group.attrs = attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct attribute_group *amd_iommu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) &amd_iommu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) &amd_iommu_cpumask_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &amd_iommu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct pmu iommu_pmu __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .event_init = perf_iommu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .add = perf_iommu_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .del = perf_iommu_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .start = perf_iommu_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .stop = perf_iommu_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .read = perf_iommu_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .attr_groups = amd_iommu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static __init int init_one_iommu(unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct perf_amd_iommu *perf_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) perf_iommu = kzalloc(sizeof(struct perf_amd_iommu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!perf_iommu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) raw_spin_lock_init(&perf_iommu->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) perf_iommu->pmu = iommu_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) perf_iommu->iommu = get_amd_iommu(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) perf_iommu->max_banks = amd_iommu_pc_get_max_banks(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) perf_iommu->max_counters = amd_iommu_pc_get_max_counters(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!perf_iommu->iommu ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) !perf_iommu->max_banks ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) !perf_iommu->max_counters) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) kfree(perf_iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snprintf(perf_iommu->name, IOMMU_NAME_SIZE, "amd_iommu_%u", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = perf_pmu_register(&perf_iommu->pmu, perf_iommu->name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pr_info("Detected AMD IOMMU #%d (%d banks, %d counters/bank).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) idx, perf_iommu->max_banks, perf_iommu->max_counters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) list_add_tail(&perf_iommu->list, &perf_amd_iommu_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pr_warn("Error initializing IOMMU %d.\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) kfree(perf_iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static __init int amd_iommu_pc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int i, cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Make sure the IOMMU PC resource is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!amd_iommu_pc_supported())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = _init_events_attrs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * An IOMMU PMU is specific to an IOMMU, and can function independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * So we go through all IOMMUs and ignore the one that fails init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * unless all IOMMU are failing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) for (i = 0; i < amd_iommu_get_num_iommus(); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = init_one_iommu(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) kfree(amd_iommu_events_group.attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Init cpumask attributes to only core 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cpumask_set_cpu(0, &iommu_cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) device_initcall(amd_iommu_pc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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