^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Performance events - AMD IBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * For licencing details see kernel-base/COPYING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../perf_event.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u32 ibs_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kprobes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/nmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * IBS states:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * and any further add()s must fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * complicated by the fact that the IBS hardware can send late NMIs (ie. after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * we've cleared the EN bit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * In order to consume these late NMIs we have the STOPPED state, any NMI that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * happens after we've cleared the EN state will clear this bit and report the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * someone else can consume our BIT and our NMI will go unhandled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * And since we cannot set/clear this separate bit together with the EN bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * there are races; if we cleared STARTED early, an NMI could land in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * could happen if the period is small enough), and consume our STOPPED bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * and trigger streams of unhandled NMIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * If, however, we clear STARTED late, an NMI can hit between clearing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * EN bit and clearing STARTED, still see STARTED set and process the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * If this event will have the VALID bit clear, we bail properly, but this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * is not a given. With VALID set we can end up calling pmu::stop() again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * (the throttle logic) and trigger the WARNs in there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * nesting, and clear STARTED late, so that we have a well defined state over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the clearing of the EN bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * XXX: we could probably be using !atomic bitops for all this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum ibs_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) IBS_ENABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IBS_STARTED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IBS_STOPPING = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IBS_STOPPED = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IBS_MAX_STATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct cpu_perf_ibs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct perf_event *event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long state[BITS_TO_LONGS(IBS_MAX_STATES)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct perf_ibs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct pmu pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u64 config_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u64 cnt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u64 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u64 valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u64 max_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long offset_mask[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int fetch_count_reset_broken : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int fetch_ignore_if_zero_rip : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct cpu_perf_ibs __percpu *pcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct attribute **format_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct attribute_group format_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const struct attribute_group *attr_groups[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 (*get_count)(u64 config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct perf_ibs_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 data[0]; /* data buffer starts here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) s64 left = local64_read(&hwc->period_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) s64 period = hwc->sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int overflow = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * If we are way outside a reasonable range then just skip forward:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (unlikely(left <= -period)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) left = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) local64_set(&hwc->period_left, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) hwc->last_period = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) overflow = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (unlikely(left < (s64)min)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) left += period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) local64_set(&hwc->period_left, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) hwc->last_period = period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) overflow = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * If the hw period that triggers the sw overflow is too short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * we might hit the irq handler. This biases the results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Thus we shorten the next-to-last period and set the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * period to the max period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (left > max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) left -= max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (left > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) left = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) else if (left < min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) left = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *hw_period = (u64)left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int shift = 64 - width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u64 prev_raw_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u64 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Careful: an NMI might modify the previous event value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Our tactic to handle this is to first atomically read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * exchange a new raw count - then add that new-prev delta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * count to the generic event atomically:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) prev_raw_count = local64_read(&hwc->prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) new_raw_count) != prev_raw_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Now we have the new raw value and have updated the prev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * timestamp already. We can now calculate the elapsed delta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * (event-)time and add that to the generic event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Careful, not all hw sign-extends above the physical width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * of the count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) delta = (new_raw_count << shift) - (prev_raw_count << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) delta >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) local64_sub(delta, &hwc->period_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct perf_ibs perf_ibs_fetch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct perf_ibs perf_ibs_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct perf_ibs *get_ibs_pmu(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (perf_ibs_fetch.pmu.type == type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return &perf_ibs_fetch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (perf_ibs_op.pmu.type == type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return &perf_ibs_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Use IBS for precise event sampling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * perf record -a -e r076:p ... # same as -e cpu-cycles:p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * perf record -a -e r0C1:p ... # use ibs op counting micro-ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * MSRC001_1033) is used to select either cycle or micro-ops counting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The rip of IBS samples has skid 0. Thus, IBS supports precise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * rip is invalid when IBS was not able to record the rip correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) switch (event->attr.precise_ip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) switch (event->attr.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case PERF_TYPE_HARDWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) switch (event->attr.config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case PERF_COUNT_HW_CPU_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case PERF_TYPE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (event->attr.config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 0x0076:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case 0x00C1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *config = IBS_OP_CNT_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int perf_ibs_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct perf_ibs *perf_ibs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u64 max_cnt, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) perf_ibs = get_ibs_pmu(event->attr.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (perf_ibs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) config = event->attr.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) perf_ibs = &perf_ibs_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = perf_ibs_precise_event(event, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (event->pmu != &perf_ibs->pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (config & ~perf_ibs->config_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (hwc->sample_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (config & perf_ibs->cnt_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* raw max_cnt may not be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * lower 4 bits can not be set in ibs max cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * but allowing it in case we adjust the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * sample period to set a frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) hwc->sample_period &= ~0x0FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!hwc->sample_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hwc->sample_period = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) max_cnt = config & perf_ibs->cnt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) config &= ~perf_ibs->cnt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) event->attr.sample_period = max_cnt << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) hwc->sample_period = event->attr.sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (!hwc->sample_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * If we modify hwc->sample_period, we also need to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * hwc->last_period and hwc->period_left.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hwc->last_period = hwc->sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) local64_set(&hwc->period_left, hwc->sample_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) hwc->config_base = perf_ibs->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hwc->config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct hw_perf_event *hwc, u64 *period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* ignore lower 4 bits in min count: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) local64_set(&hwc->prev_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static u64 get_ibs_fetch_count(u64 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return (config & IBS_FETCH_CNT) >> 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static u64 get_ibs_op_count(u64 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u64 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * If the internal 27-bit counter rolled over, the count is MaxCnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * and the lower 7 bits of CurCnt are randomized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Otherwise CurCnt has the full 27-bit current counter value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (config & IBS_OP_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) count = (config & IBS_OP_MAX_CNT) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ibs_caps & IBS_CAPS_OPCNTEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) count += config & IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else if (ibs_caps & IBS_CAPS_RDWROPCNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) count = (config & IBS_OP_CUR_CNT) >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u64 *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u64 count = perf_ibs->get_count(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Set width to 64 since we do not overflow on max width but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * instead on max count. In perf_ibs_set_period() we clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * prev count manually on overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) while (!perf_event_try_update(event, count, 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rdmsrl(event->hw.config_base, *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) count = perf_ibs->get_count(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct hw_perf_event *hwc, u64 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u64 tmp = hwc->config | config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (perf_ibs->fetch_count_reset_broken)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Erratum #420 Instruction-Based Sampling Engine May Generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Interrupt that Cannot Be Cleared:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * Must clear counter mask first, then clear the enable bit. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Revision Guide for AMD Family 10h Processors, Publication #41322.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct hw_perf_event *hwc, u64 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) config &= ~perf_ibs->cnt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (boot_cpu_data.x86 == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) wrmsrl(hwc->config_base, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) config &= ~perf_ibs->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) wrmsrl(hwc->config_base, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * We cannot restore the ibs pmu state, so we always needs to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * the event while stopping it and then reset the state when starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * perf_ibs_start()/perf_ibs_stop() and instead always do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void perf_ibs_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u64 period, config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hwc->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) perf_ibs_set_period(perf_ibs, hwc, &period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_OPCNTEXT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) config |= period & IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) period &= ~IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) config |= period >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Set STARTED before enabling the hardware, such that a subsequent NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * must observe it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) set_bit(IBS_STARTED, pcpu->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clear_bit(IBS_STOPPING, pcpu->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) perf_ibs_enable_event(perf_ibs, hwc, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void perf_ibs_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int stopping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (test_and_set_bit(IBS_STOPPING, pcpu->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) stopping = test_bit(IBS_STARTED, pcpu->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!stopping && (hwc->state & PERF_HES_UPTODATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rdmsrl(hwc->config_base, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (stopping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Set STOPPED before disabling the hardware, such that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * must be visible to NMIs the moment we clear the EN bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * at which point we can generate an !VALID sample which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * we need to consume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) set_bit(IBS_STOPPED, pcpu->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) perf_ibs_disable_event(perf_ibs, hwc, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Clear STARTED after disabling the hardware; if it were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * cleared before an NMI hitting after the clear but before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * clearing the EN bit might think it a spurious NMI and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * handle it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Clearing it after, however, creates the problem of the NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * handler seeing STARTED but not having a valid sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clear_bit(IBS_STARTED, pcpu->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hwc->state |= PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (hwc->state & PERF_HES_UPTODATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Clear valid bit to not count rollovers on update, rollovers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * are only updated in the irq handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) config &= ~perf_ibs->valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) perf_ibs_event_update(perf_ibs, event, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) hwc->state |= PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int perf_ibs_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (test_and_set_bit(IBS_ENABLED, pcpu->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pcpu->event = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) perf_ibs_start(event, PERF_EF_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void perf_ibs_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) perf_ibs_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pcpu->event = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void perf_ibs_read(struct perf_event *event) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PMU_FORMAT_ATTR(rand_en, "config:57");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PMU_FORMAT_ATTR(cnt_ctl, "config:19");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static struct attribute *ibs_fetch_format_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &format_attr_rand_en.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct attribute *ibs_op_format_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) NULL, /* &format_attr_cnt_ctl.attr if IBS_CAPS_OPCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct perf_ibs perf_ibs_fetch = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .event_init = perf_ibs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .add = perf_ibs_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .del = perf_ibs_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .start = perf_ibs_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .stop = perf_ibs_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .read = perf_ibs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .msr = MSR_AMD64_IBSFETCHCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .config_mask = IBS_FETCH_CONFIG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .cnt_mask = IBS_FETCH_MAX_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .enable_mask = IBS_FETCH_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .valid_mask = IBS_FETCH_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .max_period = IBS_FETCH_MAX_CNT << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .offset_max = MSR_AMD64_IBSFETCH_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .format_attrs = ibs_fetch_format_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .get_count = get_ibs_fetch_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct perf_ibs perf_ibs_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .task_ctx_nr = perf_invalid_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .event_init = perf_ibs_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .add = perf_ibs_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .del = perf_ibs_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .start = perf_ibs_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .stop = perf_ibs_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .read = perf_ibs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .msr = MSR_AMD64_IBSOPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .config_mask = IBS_OP_CONFIG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .cnt_mask = IBS_OP_MAX_CNT | IBS_OP_CUR_CNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) IBS_OP_CUR_CNT_RAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .enable_mask = IBS_OP_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .valid_mask = IBS_OP_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .max_period = IBS_OP_MAX_CNT << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .offset_mask = { MSR_AMD64_IBSOP_REG_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .offset_max = MSR_AMD64_IBSOP_REG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .format_attrs = ibs_op_format_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .get_count = get_ibs_op_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct perf_event *event = pcpu->event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct hw_perf_event *hwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct perf_sample_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct perf_raw_record raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct pt_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct perf_ibs_data ibs_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int offset, size, check_rip, offset_max, throttle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u64 *buf, *config, period, new_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!test_bit(IBS_STARTED, pcpu->state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Catch spurious interrupts after stopping IBS: After
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * disabling IBS there could be still incoming NMIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * with samples that even have the valid bit cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Mark all this NMIs as handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (WARN_ON_ONCE(!event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) msr = hwc->config_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) buf = ibs_data.regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) rdmsrl(msr, *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!(*buf++ & perf_ibs->valid_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) config = &ibs_data.regs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) perf_ibs_event_update(perf_ibs, event, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) perf_sample_data_init(&data, 0, hwc->last_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!perf_ibs_set_period(perf_ibs, hwc, &period))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) goto out; /* no sw counter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ibs_data.caps = ibs_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) offset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (event->attr.sample_type & PERF_SAMPLE_RAW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) offset_max = perf_ibs->offset_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else if (check_rip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) offset_max = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) offset_max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rdmsrl(msr + offset, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) offset = find_next_bit(perf_ibs->offset_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) perf_ibs->offset_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) offset + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } while (offset < offset_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * depending on their availability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Can't add to offset_max as they are staggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (event->attr.sample_type & PERF_SAMPLE_RAW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (perf_ibs == &perf_ibs_op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ibs_caps & IBS_CAPS_BRNTRGT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ibs_caps & IBS_CAPS_OPDATA4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ibs_data.size = sizeof(u64) * size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regs = *iregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regs.flags &= ~PERF_EFLAGS_EXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Workaround for erratum #1197 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (perf_ibs->fetch_ignore_if_zero_rip && !(ibs_data.regs[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) set_linear_ip(®s, ibs_data.regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) regs.flags |= PERF_EFLAGS_EXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (event->attr.sample_type & PERF_SAMPLE_RAW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) raw = (struct perf_raw_record){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .frag = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .size = sizeof(u32) + ibs_data.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .data = ibs_data.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) data.raw = &raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) throttle = perf_event_overflow(event, &data, ®s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (throttle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) perf_ibs_stop(event, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (perf_ibs == &perf_ibs_op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ibs_caps & IBS_CAPS_OPCNTEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) new_config = period & IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) period &= ~IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if ((ibs_caps & IBS_CAPS_RDWROPCNT) && (*config & IBS_OP_CNT_CTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) new_config |= *config & IBS_OP_CUR_CNT_RAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) new_config |= period >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) perf_ibs_enable_event(perf_ibs, hwc, new_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u64 stamp = sched_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) inc_irq_stat(apic_perf_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) perf_sample_event_took(sched_clock() - stamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct cpu_perf_ibs __percpu *pcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pcpu = alloc_percpu(struct cpu_perf_ibs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!pcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) perf_ibs->pcpu = pcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* register attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (perf_ibs->format_attrs[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) memset(&perf_ibs->format_group, 0, sizeof(perf_ibs->format_group));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) perf_ibs->format_group.name = "format";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) perf_ibs->format_group.attrs = perf_ibs->format_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) memset(&perf_ibs->attr_groups, 0, sizeof(perf_ibs->attr_groups));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) perf_ibs->attr_groups[0] = &perf_ibs->format_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) perf_ibs->pmu.attr_groups = perf_ibs->attr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) perf_ibs->pcpu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) free_percpu(pcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static __init void perf_event_ibs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct attribute **attr = ibs_op_format_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * Some chips fail to reset the fetch count when it is written; instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * they need a 0-1 transition of IbsFetchEn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (boot_cpu_data.x86 >= 0x16 && boot_cpu_data.x86 <= 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) perf_ibs_fetch.fetch_count_reset_broken = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ibs_caps & IBS_CAPS_OPCNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *attr++ = &format_attr_cnt_ctl.attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ibs_caps & IBS_CAPS_OPCNTEXT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) perf_ibs_op.max_period |= IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) perf_ibs_op.config_mask |= IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static __init void perf_event_ibs_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* IBS - apic initialization, for perf and oprofile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static __init u32 __get_ibs_caps(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned int max_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!boot_cpu_has(X86_FEATURE_IBS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* check IBS cpuid feature flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) max_level = cpuid_eax(0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (max_level < IBS_CPUID_FEATURES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return IBS_CAPS_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) caps = cpuid_eax(IBS_CPUID_FEATURES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!(caps & IBS_CAPS_AVAIL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* cpuid flags not valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return IBS_CAPS_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 get_ibs_caps(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ibs_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) EXPORT_SYMBOL(get_ibs_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static inline int get_eilvt(int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static inline int put_eilvt(int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return !setup_APIC_eilvt(offset, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * Check and reserve APIC extended interrupt LVT offset for IBS if available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static inline int ibs_eilvt_valid(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) rdmsrl(MSR_AMD64_IBSCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) offset = val & IBSCTL_LVT_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!get_eilvt(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int setup_ibs_ctl(int ibs_eilvt_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct pci_dev *cpu_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) nodes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) cpu_cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PCI_DEVICE_ID_AMD_10H_NB_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) cpu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!cpu_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ++nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) | IBSCTL_LVT_OFFSET_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pci_read_config_dword(cpu_cfg, IBSCTL, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pci_dev_put(cpu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!nodes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pr_debug("No CPU node configured for IBS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * This runs only on the current cpu. We try to find an LVT offset and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * setup the local APIC. For this we must disable preemption. On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * success we initialize all nodes with this offset. This updates then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * is using the new offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void force_ibs_eilvt_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* find the next free available EILVT entry, skip offset 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (get_eilvt(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (offset == APIC_EILVT_NR_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pr_debug("No EILVT entry available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = setup_ibs_ctl(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!ibs_eilvt_valid())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pr_info("LVT offset %d assigned\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) put_eilvt(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static void ibs_eilvt_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * Force LVT offset assignment for family 10h: The offsets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * not assigned by the BIOS for this family, so the OS is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * responsible for doing it. If the OS assignment fails, fall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * back to BIOS settings and try to setup this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (boot_cpu_data.x86 == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) force_ibs_eilvt_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static inline int get_ibs_lvt_offset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) rdmsrl(MSR_AMD64_IBSCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!(val & IBSCTL_LVT_OFFSET_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return val & IBSCTL_LVT_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static void setup_APIC_ibs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) offset = get_ibs_lvt_offset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void clear_APIC_ibs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) offset = get_ibs_lvt_offset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (offset >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) setup_APIC_ibs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int perf_ibs_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) clear_APIC_ibs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static void perf_ibs_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ibs_eilvt_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) setup_APIC_ibs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static struct syscore_ops perf_ibs_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .resume = perf_ibs_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .suspend = perf_ibs_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static void perf_ibs_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) register_syscore_ops(&perf_ibs_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static inline void perf_ibs_pm_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) clear_APIC_ibs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static __init int amd_ibs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) caps = __get_ibs_caps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (!caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return -ENODEV; /* ibs not supported by the cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ibs_eilvt_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!ibs_eilvt_valid())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) perf_ibs_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ibs_caps = caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* make ibs_caps visible to other cpus: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) smp_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * x86_pmu_amd_ibs_starting_cpu will be called from core on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * all online cpus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "perf/x86/amd/ibs:starting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) x86_pmu_amd_ibs_starting_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) x86_pmu_amd_ibs_dying_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) perf_event_ibs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Since we need the pci subsystem to init ibs we can't do this earlier: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) device_initcall(amd_ibs_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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