Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Using hardware provided CRC32 instruction to accelerate the CRC32 disposal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * CRC32C polynomial:0x1EDC6F41(BE)/0x82F63B78(LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * CRC32 is a new instruction in Intel SSE4.2, the reference can be found at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * http://www.intel.com/products/processor/manuals/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Intel(R) 64 and IA-32 Architectures Software Developer's Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Volume 2A: Instruction Set Reference, A-M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2008 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Authors: Austin Zhang <austin_zhang@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *          Kent Liu <kent.liu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <crypto/internal/simd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/cpufeatures.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/simd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CHKSUM_BLOCK_SIZE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CHKSUM_DIGEST_SIZE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCALE_F	sizeof(unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CRC32_INST "crc32q %1, %q0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CRC32_INST "crc32l %1, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * use carryless multiply version of crc32c when buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * size is >= 512 to account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * for fpu state save/restore overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CRC32C_PCL_BREAKEVEN	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) asmlinkage unsigned int crc_pcl(const u8 *buffer, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				unsigned int crc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #endif /* CONFIG_X86_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static u32 crc32c_intel_le_hw_byte(u32 crc, unsigned char const *data, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	while (length--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		asm("crc32b %1, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		    : "+r" (crc) : "rm" (*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static u32 __pure crc32c_intel_le_hw(u32 crc, unsigned char const *p, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int iquotient = len / SCALE_F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned int iremainder = len % SCALE_F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned long *ptmp = (unsigned long *)p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	while (iquotient--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		asm(CRC32_INST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		    : "+r" (crc) : "rm" (*ptmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		ptmp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (iremainder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		crc = crc32c_intel_le_hw_byte(crc, (unsigned char *)ptmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				 iremainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * Setting the seed allows arbitrary accumulators and flexible XOR policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * If your algorithm starts with ~0, then XOR with ~0 before you set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * the seed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int crc32c_intel_setkey(struct crypto_shash *hash, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 *mctx = crypto_shash_ctx(hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (keylen != sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	*mctx = le32_to_cpup((__le32 *)key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int crc32c_intel_init(struct shash_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 *mctx = crypto_shash_ctx(desc->tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 *crcp = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	*crcp = *mctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int crc32c_intel_update(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			       unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 *crcp = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	*crcp = crc32c_intel_le_hw(*crcp, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int __crc32c_intel_finup(u32 *crcp, const u8 *data, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 				u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	*(__le32 *)out = ~cpu_to_le32(crc32c_intel_le_hw(*crcp, data, len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int crc32c_intel_finup(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			      unsigned int len, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return __crc32c_intel_finup(shash_desc_ctx(desc), data, len, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int crc32c_intel_final(struct shash_desc *desc, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 *crcp = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	*(__le32 *)out = ~cpu_to_le32p(crcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int crc32c_intel_digest(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			       unsigned int len, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return __crc32c_intel_finup(crypto_shash_ctx(desc->tfm), data, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				    out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int crc32c_intel_cra_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 *key = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	*key = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int crc32c_pcl_intel_update(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			       unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 *crcp = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 * use faster PCL version if datasize is large enough to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * overcome kernel fpu state save/restore overhead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (len >= CRC32C_PCL_BREAKEVEN && crypto_simd_usable()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		kernel_fpu_begin();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		*crcp = crc_pcl(data, len, *crcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		kernel_fpu_end();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		*crcp = crc32c_intel_le_hw(*crcp, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int __crc32c_pcl_intel_finup(u32 *crcp, const u8 *data, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (len >= CRC32C_PCL_BREAKEVEN && crypto_simd_usable()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		kernel_fpu_begin();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		*(__le32 *)out = ~cpu_to_le32(crc_pcl(data, len, *crcp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		kernel_fpu_end();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		*(__le32 *)out =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			~cpu_to_le32(crc32c_intel_le_hw(*crcp, data, len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int crc32c_pcl_intel_finup(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			      unsigned int len, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return __crc32c_pcl_intel_finup(shash_desc_ctx(desc), data, len, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int crc32c_pcl_intel_digest(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			       unsigned int len, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return __crc32c_pcl_intel_finup(crypto_shash_ctx(desc->tfm), data, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				    out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif /* CONFIG_X86_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct shash_alg alg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.setkey			=	crc32c_intel_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.init			=	crc32c_intel_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.update			=	crc32c_intel_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.final			=	crc32c_intel_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.finup			=	crc32c_intel_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.digest			=	crc32c_intel_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.descsize		=	sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.digestsize		=	CHKSUM_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.base			=	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.cra_name		=	"crc32c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.cra_driver_name	=	"crc32c-intel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.cra_priority		=	200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.cra_flags		=	CRYPTO_ALG_OPTIONAL_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.cra_blocksize		=	CHKSUM_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.cra_ctxsize		=	sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.cra_module		=	THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.cra_init		=	crc32c_intel_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct x86_cpu_id crc32c_cpu_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int __init crc32c_intel_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!x86_match_cpu(crc32c_cpu_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		alg.update = crc32c_pcl_intel_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		alg.finup = crc32c_pcl_intel_finup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		alg.digest = crc32c_pcl_intel_digest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return crypto_register_shash(&alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __exit crc32c_intel_mod_fini(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	crypto_unregister_shash(&alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) module_init(crc32c_intel_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) module_exit(crc32c_intel_mod_fini);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_AUTHOR("Austin Zhang <austin.zhang@intel.com>, Kent Liu <kent.liu@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_DESCRIPTION("CRC32c (Castagnoli) optimization using Intel Hardware.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_ALIAS_CRYPTO("crc32c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_ALIAS_CRYPTO("crc32c-intel");