^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* -*- linux-c -*- ------------------------------------------------------- *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1991, 1992 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007 rPath, Inc. - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Check for obligatory CPU features and abort if the features are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * present. This code should be compilable as 16-, 32- or 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * code, so be very careful with types and inline assembly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This code should not contain any messages; that requires an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * additional wrapper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * As written, this code is not safe for inclusion into the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * proper (after FPU initialization, in particular).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef _SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # include "boot.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/intel-family.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/processor-flags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/required-features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/msr-index.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "string.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static u32 err_flags[NCAPINTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const u32 req_flags[NCAPINTS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) REQUIRED_MASK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) REQUIRED_MASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0, /* REQUIRED_MASK2 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0, /* REQUIRED_MASK3 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) REQUIRED_MASK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0, /* REQUIRED_MASK5 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) REQUIRED_MASK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0, /* REQUIRED_MASK7 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0, /* REQUIRED_MASK8 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0, /* REQUIRED_MASK9 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0, /* REQUIRED_MASK10 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0, /* REQUIRED_MASK11 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0, /* REQUIRED_MASK12 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0, /* REQUIRED_MASK13 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0, /* REQUIRED_MASK14 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0, /* REQUIRED_MASK15 not implemented in this file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) REQUIRED_MASK16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int is_amd(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cpu_vendor[2] == A32('c', 'A', 'M', 'D');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int is_centaur(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cpu_vendor[2] == A32('a', 'u', 'l', 's');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int is_transmeta(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cpu_vendor[2] == A32('M', 'x', '8', '6');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int is_intel(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cpu_vendor[1] == A32('i', 'n', 'e', 'I') &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) cpu_vendor[2] == A32('n', 't', 'e', 'l');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Returns a bitmask of which words we have error bits in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int check_cpuflags(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < NCAPINTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) err_flags[i] = req_flags[i] & ~cpu.flags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (err_flags[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) err |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Returns -1 on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * *cpu_level is set to the current CPU level; *req_level to the required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * level. x86-64 is considered level 64 for this purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * *err_flags_ptr is set to the flags error array if there are flags missing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) memset(&cpu.flags, 0, sizeof(cpu.flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpu.level = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (has_eflag(X86_EFLAGS_AC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cpu.level = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) get_cpuflags();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err = check_cpuflags();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (test_bit(X86_FEATURE_LM, cpu.flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cpu.level = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (err == 0x01 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) !(err_flags[0] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) is_amd()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* If this is an AMD and we're only missing SSE+SSE2, try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) turn them on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 ecx = MSR_K7_HWCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 eax, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) eax &= ~(1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) get_cpuflags(); /* Make sure it really did something */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) err = check_cpuflags();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } else if (err == 0x01 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) is_centaur() && cpu.model >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* If this is a VIA C3, we might have to enable CX8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) explicitly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 ecx = MSR_VIA_FCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 eax, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) eax |= (1<<1)|(1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) set_bit(X86_FEATURE_CX8, cpu.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) err = check_cpuflags();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else if (err == 0x01 && is_transmeta()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Transmeta might have masked feature bits in word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 ecx = 0x80860004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 eax, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 level = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) asm("cpuid"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) : "+a" (level), "=d" (cpu.flags[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) : : "ecx", "ebx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err = check_cpuflags();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else if (err == 0x01 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) !(err_flags[0] & ~(1 << X86_FEATURE_PAE)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) is_intel() && cpu.level == 6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (cpu.model == 9 || cpu.model == 13)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* PAE is disabled on this Pentium M but can be forced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (cmdline_find_option_bool("forcepae")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) puts("WARNING: Forcing PAE in CPU flags\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) set_bit(X86_FEATURE_PAE, cpu.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err = check_cpuflags();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) puts("WARNING: PAE disabled. Use parameter 'forcepae' to enable at your own risk!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) err = check_knl_erratum();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (err_flags_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *err_flags_ptr = err ? err_flags : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (cpu_level_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *cpu_level_ptr = cpu.level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (req_level_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *req_level_ptr = req_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return (cpu.level < req_level || err) ? -1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int check_knl_erratum(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * First check for the affected model/family:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!is_intel() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cpu.family != 6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cpu.model != INTEL_FAM6_XEON_PHI_KNL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * This erratum affects the Accessed/Dirty bits, and can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * cause stray bits to be set in !Present PTEs. We have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * enough bits in our 64-bit PTEs (which we have on real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 64-bit mode or PAE) to avoid using these troublesome
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * bits. But, we do not have enough space in our 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * PTEs. So, refuse to run on 32-bit non-PAE kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (IS_ENABLED(CONFIG_X86_64) || IS_ENABLED(CONFIG_X86_PAE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) puts("This 32-bit kernel can not run on this Xeon Phi x200\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "processor due to a processor erratum. Use a 64-bit\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "kernel, or enable PAE in this 32-bit kernel.\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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