^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sparc64/math-emu/sfp-util.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __asm__ ("addcc %4,%5,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "add %2,%3,%0\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "bcs,a,pn %%xcc, 1f\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "add %0, 1, %0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "1:" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) : "r" ((UDItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "r" ((UDItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "r" ((UDItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "r" ((UDItype)(bl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) : "cc")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __asm__ ("subcc %4,%5,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "sub %2,%3,%0\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "bcs,a,pn %%xcc, 1f\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "sub %0, 1, %0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "1:" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) : "=r" (sh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "=&r" (sl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) : "r" ((UDItype)(ah)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "r" ((UDItype)(bh)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "r" ((UDItype)(al)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "r" ((UDItype)(bl)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) : "cc")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define umul_ppmm(wh, wl, u, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) UDItype tmp1, tmp2, tmp3, tmp4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __asm__ __volatile__ ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "srl %7,0,%3\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "mulx %3,%6,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "srlx %6,32,%2\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "mulx %2,%3,%4\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "sllx %4,32,%5\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "srl %6,0,%3\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "sub %1,%5,%5\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "srlx %5,32,%5\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "addcc %4,%5,%4\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "srlx %7,32,%5\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "mulx %3,%5,%3\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "mulx %2,%5,%5\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "sethi %%hi(0x80000000),%2\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "addcc %4,%3,%4\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "srlx %4,32,%4\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "add %2,%2,%2\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "movcc %%xcc,%%g0,%2\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "addcc %5,%4,%5\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "sllx %3,32,%3\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "add %1,%3,%1\n\t" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "add %5,%2,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) : "=r" (wh), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "=&r" (wl), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) : "r" ((UDItype)(u)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "r" ((UDItype)(v)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) : "cc"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define udiv_qrnnd(q, r, n1, n0, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __d1 = (d >> 32); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __d0 = (USItype)d; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __r1 = (n1) % __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __q1 = (n1) / __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __m = (UWtype) __q1 * __d0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __r1 = (__r1 << 32) | (n0 >> 32); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (__r1 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __q1--, __r1 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (__r1 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __q1--, __r1 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __r1 -= __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __r0 = __r1 % __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __q0 = __r1 / __d1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __m = (UWtype) __q0 * __d0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __r0 = (__r0 << 32) | ((USItype)n0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (__r0 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __q0--, __r0 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (__r0 >= (d)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (__r0 < __m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __q0--, __r0 += (d); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __r0 -= __m; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (q) = (UWtype) (__q1 << 32) | __q0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (r) = __r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define UDIV_NEEDS_NORMALIZATION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define abort() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define __BYTE_ORDER __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define __BYTE_ORDER __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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