^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sparc64/math-emu/math.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Emulation routines originate from soft-fp package, which is part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * of glibc and has appropriate copyrights in it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/fpumacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "sfp-util_64.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <math-emu/soft-fp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <math-emu/single.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <math-emu/double.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <math-emu/quad.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* QUAD - ftt == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FMOVQ 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FNEGQ 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FABSQ 0x00b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSQRTQ 0x02b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FADDQ 0x043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSUBQ 0x047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FMULQ 0x04b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FDIVQ 0x04f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FDMULQ 0x06e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FQTOX 0x083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FXTOQ 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FQTOS 0x0c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FQTOD 0x0cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FITOQ 0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSTOQ 0x0cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FDTOQ 0x0ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FQTOI 0x0d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* SUBNORMAL - ftt == 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FSQRTS 0x029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FSQRTD 0x02a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FADDS 0x041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FADDD 0x042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FSUBS 0x045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FSUBD 0x046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FMULS 0x049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FMULD 0x04a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FDIVS 0x04d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FDIVD 0x04e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FSMULD 0x069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FSTOX 0x081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FDTOX 0x082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FDTOS 0x0c6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FSTOD 0x0c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FSTOI 0x0d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FDTOI 0x0d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FXTOS 0x084 /* Only Ultra-III generates this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FXTOD 0x088 /* Only Ultra-III generates this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #if 0 /* Optimized inline in sparc64/kernel/entry.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FITOS 0x0c4 /* Only Ultra-III generates this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FITOD 0x0c8 /* Only Ultra-III generates this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* FPOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FCMPQ 0x053
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FCMPEQ 0x057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FMOVQ0 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FMOVQ1 0x043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FMOVQ2 0x083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FMOVQ3 0x0c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FMOVQI 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FMOVQX 0x183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FMOVQZ 0x027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FMOVQLE 0x047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FMOVQLZ 0x067
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FMOVQNZ 0x0a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FMOVQGZ 0x0c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FMOVQGE 0x0e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FSR_TEM_SHIFT 23UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FSR_AEXC_SHIFT 5UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FSR_CEXC_SHIFT 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* All routines returning an exception to raise should detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * such exceptions _before_ rounding to be consistent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * the behavior of the hardware in the implemented cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * (and thus with the recommendations in the V9 architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * manual).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * We return 0 if a SIGFPE should be sent, 1 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline int record_exception(struct pt_regs *regs, int eflag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u64 fsr = current_thread_info()->xfsr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int would_trap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Determine if this exception would have generated a trap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* If trapping, we only want to signal one bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if(would_trap != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if((eflag & (eflag - 1)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if(eflag & FP_EX_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) eflag = FP_EX_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) else if(eflag & FP_EX_OVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) eflag = FP_EX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else if(eflag & FP_EX_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) eflag = FP_EX_UNDERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else if(eflag & FP_EX_DIVZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) eflag = FP_EX_DIVZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else if(eflag & FP_EX_INEXACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) eflag = FP_EX_INEXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Set CEXC, here is the rule:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * In general all FPU ops will set one and only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * bit in the CEXC field, this is always the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * when the IEEE exception trap is enabled in TEM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) fsr &= ~(FSR_CEXC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) fsr |= ((long)eflag << FSR_CEXC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Set the AEXC field, rule is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * If a trap would not be generated, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * CEXC just generated is OR'd into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * existing value of AEXC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if(would_trap == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) fsr |= ((long)eflag << FSR_AEXC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* If trapping, indicate fault trap type IEEE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if(would_trap != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fsr |= (1UL << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) current_thread_info()->xfsr[0] = fsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* If we will not trap, advance the program counter over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the instruction being handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if(would_trap == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regs->tpc = regs->tnpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regs->tnpc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return (would_trap ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u64 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u64 q[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } *argp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long pc = regs->tpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long tstate = regs->tstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 insn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int freg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static u64 zero[2] = { 0L, 0L };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FP_DECL_EX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int IR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) long XR, xfsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (tstate & TSTATE_PRIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (test_thread_flag(TIF_32BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pc = (u32)pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) switch ((insn >> 5) & 0x1ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* QUAD - ftt == 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case FMOVQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case FNEGQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case FABSQ: TYPE(3,3,0,3,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case FADDQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case FSUBQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case FMULQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case FQTOX: TYPE(3,2,0,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case FQTOS: TYPE(3,1,1,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case FQTOD: TYPE(3,2,1,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case FITOQ: TYPE(3,3,1,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case FQTOI: TYPE(3,1,0,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* We can get either unimplemented or unfinished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * for these cases. Pre-Niagara systems generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * unfinished fpop for SUBNORMAL cases, and Niagara
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * always gives unimplemented fpop for fsqrt{s,d}.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case FSQRTS: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long x = current_thread_info()->xfsr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) x = (x >> 14) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) TYPE(x,1,1,1,1,0,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case FSQRTD: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long x = current_thread_info()->xfsr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) x = (x >> 14) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) TYPE(x,2,1,2,1,0,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* SUBNORMAL - ftt == 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case FADDD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case FSUBD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case FMULD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case FDIVD: TYPE(2,2,1,2,1,2,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case FADDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case FSUBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case FMULS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case FDIVS: TYPE(2,1,1,1,1,1,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case FSMULD: TYPE(2,2,1,1,1,1,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case FSTOX: TYPE(2,2,0,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case FDTOX: TYPE(2,2,0,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case FDTOS: TYPE(2,1,1,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case FSTOD: TYPE(2,2,1,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case FSTOI: TYPE(2,1,0,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case FDTOI: TYPE(2,1,0,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Only Ultra-III generates these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case FXTOS: TYPE(2,1,1,2,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case FXTOD: TYPE(2,2,1,2,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #if 0 /* Optimized inline in sparc64/kernel/entry.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case FITOS: TYPE(2,1,1,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case FITOD: TYPE(2,2,1,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IR = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) switch ((insn >> 5) & 0x1ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Now the conditional fmovq support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case FMOVQ0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case FMOVQ1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case FMOVQ2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case FMOVQ3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* fmovq %fccX, %fY, %fZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!((insn >> 11) & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) XR = current_thread_info()->xfsr[0] >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) XR = current_thread_info()->xfsr[0] >> (30 + ((insn >> 10) & 0x6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) XR &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch ((insn >> 14) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* case 0: IR = 0; break; */ /* Never */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 1: if (XR) IR = 1; break; /* Not Equal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case 2: if (XR == 1 || XR == 2) IR = 1; break; /* Less or Greater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case 4: if (XR == 1) IR = 1; break; /* Less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 6: if (XR == 2) IR = 1; break; /* Greater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case 7: if (XR == 3) IR = 1; break; /* Unordered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if ((insn >> 14) & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IR ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case FMOVQI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case FMOVQX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* fmovq %[ix]cc, %fY, %fZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) XR = regs->tstate >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if ((insn >> 5) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) XR >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) XR &= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) IR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) freg = ((XR >> 2) ^ XR) & 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch ((insn >> 14) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* case 0: IR = 0; break; */ /* Never */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case 1: if (XR & 4) IR = 1; break; /* Equal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case 2: if ((XR & 4) || freg) IR = 1; break; /* Less or Equal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 3: if (freg) IR = 1; break; /* Less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case 5: if (XR & 1) IR = 1; break; /* Carry Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 6: if (XR & 8) IR = 1; break; /* Negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case 7: if (XR & 2) IR = 1; break; /* Overflow Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if ((insn >> 14) & 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) IR ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case FMOVQZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case FMOVQLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case FMOVQLZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case FMOVQNZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case FMOVQGZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case FMOVQGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) freg = (insn >> 14) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!freg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) XR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else if (freg < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) XR = regs->u_regs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct reg_window32 __user *win32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) flushw_user ();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) win32 = (struct reg_window32 __user *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) get_user(XR, &win32->locals[freg - 16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct reg_window __user *win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) flushw_user ();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) win = (struct reg_window __user *)(regs->u_regs[UREG_FP] + STACK_BIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) get_user(XR, &win->locals[freg - 16]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) IR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch ((insn >> 10) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 1: if (!XR) IR = 1; break; /* Register Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if ((insn >> 10) & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) IR ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (IR == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* The fmov test was false. Do a nop instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regs->tpc = regs->tnpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) regs->tnpc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } else if (IR == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Change the instruction into plain fmovq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) insn = (insn & 0x3e00001f) | 0x81a00060;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) TYPE(3,3,0,3,0,0,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) argp rs1 = NULL, rs2 = NULL, rd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Starting with UltraSPARC-T2, the cpu does not set the FP Trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Type field in the %fsr to unimplemented_FPop. Nor does it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * use the fp_exception_other trap. Instead it signals an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * illegal instruction and leaves the FP trap type field of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * the %fsr unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!illegal_insn_trap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ftt = (current_thread_info()->xfsr[0] >> 14) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ftt != (type >> 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) current_thread_info()->xfsr[0] &= ~0x1c000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) freg = ((insn >> 14) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (type & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 3: if (freg & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case 1: rs1 = (argp)&f->regs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) flags = (freg < 32) ? FPRS_DL : FPRS_DU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!(current_thread_info()->fpsaved[0] & flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rs1 = (argp)&zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) switch (type & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 7: FP_UNPACK_QP (QA, rs1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case 6: FP_UNPACK_DP (DA, rs1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case 5: FP_UNPACK_SP (SA, rs1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) freg = (insn & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch ((type >> 3) & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case 3: if (freg & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 1: rs2 = (argp)&f->regs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) flags = (freg < 32) ? FPRS_DL : FPRS_DU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!(current_thread_info()->fpsaved[0] & flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rs2 = (argp)&zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) switch ((type >> 3) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case 7: FP_UNPACK_QP (QB, rs2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 6: FP_UNPACK_DP (DB, rs2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case 5: FP_UNPACK_SP (SB, rs2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) freg = ((insn >> 25) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) switch ((type >> 6) & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case 3: if (freg & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case 1: rd = (argp)&f->regs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) flags = (freg < 32) ? FPRS_DL : FPRS_DU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) current_thread_info()->fpsaved[0] = FPRS_FEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) current_thread_info()->gsr[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!(current_thread_info()->fpsaved[0] & flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (freg < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) memset(f->regs, 0, 32*sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) memset(f->regs+32, 0, 32*sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) current_thread_info()->fpsaved[0] |= flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) switch ((insn >> 5) & 0x1ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* + */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case FADDS: FP_ADD_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case FADDD: FP_ADD_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case FADDQ: FP_ADD_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case FSUBS: FP_SUB_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) case FSUBD: FP_SUB_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case FMULS: FP_MUL_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FP_CONV (D, S, 1, 1, DB, SB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case FMULD: FP_MUL_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) FP_CONV (Q, D, 2, 1, QB, DB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case FMULQ: FP_MUL_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* / */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case FDIVS: FP_DIV_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case FDIVD: FP_DIV_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* sqrt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case FSQRTS: FP_SQRT_S (SR, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case FSQRTD: FP_SQRT_D (DR, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case FSQRTQ: FP_SQRT_Q (QR, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* mov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* float to int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* int to float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Only Ultra-III generates these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #if 0 /* Optimized inline in sparc64/kernel/entry.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* float to float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case FCMPQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case FCMPEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) FP_CMP_Q(XR, QB, QA, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (XR == 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (((insn >> 5) & 0x1ff) == FCMPEQ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) FP_ISSIGNAN_Q(QA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FP_ISSIGNAN_Q(QB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) FP_SET_EXCEPTION (FP_EX_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!FP_INHIBIT_RESULTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) switch ((type >> 6) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case 0: xfsr = current_thread_info()->xfsr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (XR == -1) XR = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) switch (freg & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* fcc0, 1, 2, 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) current_thread_info()->xfsr[0] = xfsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case 1: rd->s = IR; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case 2: rd->d = XR; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case 5: FP_PACK_SP (rd, SR); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case 6: FP_PACK_DP (rd, DR); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case 7: FP_PACK_QP (rd, QR); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if(_fex != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return record_exception(regs, _fex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Success and no exceptions detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) current_thread_info()->xfsr[0] &= ~(FSR_CEXC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) regs->tpc = regs->tnpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regs->tnpc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) err: return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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