^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sparc/math-emu/math.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This is a good place to start if you're trying to understand the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * emulation code, because it's pretty simple. What we do is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * essentially analyse the instruction to work out what the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * is and which registers are involved. We then execute the appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * FXXXX function. [The floating point queue introduces a minor wrinkle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * see below...]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The fxxxxx.c files each emulate a single insn. They look relatively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * simple because the complexity is hidden away in an unholy tangle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * of preprocessor macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The first layer of macros is single.h, double.h, quad.h. Generally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * these files define macros for working with floating point numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * for instance. These macros are usually defined as calls to more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * of machine words required to store the given IEEE format is passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * as a parameter. [double.h and co check the number of bits in a word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * and define FP_ADD_D & co appropriately].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The generic macros are defined in op-common.h. This is where all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the grotty stuff like handling NaNs is coded. To handle the possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * where wc is the 'number of machine words' parameter (here 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * These are defined in the third layer of macros: op-1.h, op-2.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * and op-4.h. These handle operations on floating point numbers composed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * of 1,2 and 4 machine words respectively. [For example, on sparc64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * doubles are one machine word so macros in double.h eventually use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * soft-fp.h is on the same level as op-common.h, and defines some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * macros which are independent of both word size and FP format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Finally, sfp-machine.h is the machine dependent part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * code: it defines the word size and what type a word is. It also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * provide several possible flavours of multiply algorithm, most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * of which require that you supply some form of asm or C primitive to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * do the actual multiply. (such asm primitives should be defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * in sfp-machine.h too). udivmodti4.c is the same sort of thing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * There may be some errors here because I'm working from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * SPARC architecture manual V9, and what I really want is V8...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Also, the insns which can generate exceptions seem to be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * greater subset of the FPops than for V9 (for example, FCMPED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * has to be emulated on V8). So I think I'm going to have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * to emulate them all just to be on the safe side...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Emulation routines originate from soft-fp package, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * part of glibc and has appropriate copyrights in it (allegedly).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * NB: on sparc int == long == 4 bytes, long long == 8 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Most bits of the kernel seem to go for long rather than int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * so we follow that practice...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * fpsave() saves the FP queue but fpload() doesn't reload it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Therefore when we context switch or change FPU ownership
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * we have to check to see if the queue had anything in it and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * emulate it if it did. This is going to be a pain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include "sfp-util_32.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <math-emu/soft-fp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <math-emu/single.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <math-emu/double.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <math-emu/quad.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FLOATFUNC(x) extern int x(void *,void *,void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* The Vn labels indicate what version of the SPARC architecture gas thinks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * each insn is. This is from the binutils source :->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* quadword instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FSQRTQ 0x02b /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FADDQ 0x043 /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FSUBQ 0x047 /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FMULQ 0x04b /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FDIVQ 0x04f /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FDMULQ 0x06e /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FQTOS 0x0c7 /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FQTOD 0x0cb /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FITOQ 0x0cc /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FSTOQ 0x0cd /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FDTOQ 0x0ce /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FQTOI 0x0d3 /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FCMPQ 0x053 /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FCMPEQ 0x057 /* v8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* single/double instructions (subnormal): should all work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FSQRTS 0x029 /* v7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FSQRTD 0x02a /* v7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FADDS 0x041 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FADDD 0x042 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FSUBS 0x045 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FSUBD 0x046 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FMULS 0x049 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FMULD 0x04a /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FDIVS 0x04d /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FDIVD 0x04e /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FSMULD 0x069 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FDTOS 0x0c6 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FSTOD 0x0c9 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FSTOI 0x0d1 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FDTOI 0x0d2 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FABSS 0x009 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FCMPS 0x051 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FCMPES 0x055 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FCMPD 0x052 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FCMPED 0x056 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FMOVS 0x001 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FNEGS 0x005 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FITOS 0x0c4 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FITOD 0x0c8 /* v6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FSR_TEM_SHIFT 23UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FSR_AEXC_SHIFT 5UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FSR_CEXC_SHIFT 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Unlike the Sparc64 version (which has a struct fpustate), we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * pass the taskstruct corresponding to the task which currently owns the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * FPU. This is partly because we don't have the fpustate struct and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * partly because the task owning the FPU isn't always current (as is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * the case for the Sparc64 port). This is probably SMP-related...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * This function returns 1 if all queued insns were emulated successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * The test for unimplemented FPop in kernel mode has been moved into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * kernel/traps.c for simplicity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* regs->pc isn't necessarily the PC at which the offending insn is sitting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * The FPU maintains a queue of FPops which cause traps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * When it hits an instruction that requires that the trapped op succeeded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * (usually because it reads a reg. that the trapped op wrote) then it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * causes this exception. We need to emulate all the insns on the queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * and then allow the op to proceed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * This code should also handle the case where the trap was precise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * in which case the queue length is zero and regs->pc points at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * single FPop to be emulated. (this case is untested, though :->)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * You'll need this case if you want to be able to emulate all FPops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * because the FPU either doesn't exist or has been software-disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * might sound because the Ultra does funky things with a superscalar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * architecture.]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int retcode = 0; /* assume all succeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef DEBUG_MATHEMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) printk("In do_mathemu()... pc is %08lx\n", regs->pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) for (i = 0; i < fpt->thread.fpqdepth; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (unsigned long)fpt->thread.fpqueue[i].insn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (fpt->thread.fpqdepth == 0) { /* no queue, guilty insn is at regs->pc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #ifdef DEBUG_MATHEMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) printk("precise trap at %08lx\n", regs->pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!get_user(insn, (u32 __user *) regs->pc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (retcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* in this case we need to fix up PC & nPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) regs->pc = regs->npc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) regs->npc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return retcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Normal case: need to empty the queue... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < fpt->thread.fpqdepth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!retcode) /* insn failed, no point doing any more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Now empty the queue and clear the queue_not_empty flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (retcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) fpt->thread.fsr &= ~0x3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) fpt->thread.fpqdepth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return retcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* All routines returning an exception to raise should detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * such exceptions _before_ rounding to be consistent with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * the behavior of the hardware in the implemented cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * (and thus with the recommendations in the V9 architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * manual).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * We return 0 if a SIGFPE should be sent, 1 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline int record_exception(unsigned long *pfsr, int eflag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long fsr = *pfsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int would_trap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Determine if this exception would have generated a trap. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* If trapping, we only want to signal one bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (would_trap != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if ((eflag & (eflag - 1)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (eflag & FP_EX_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) eflag = FP_EX_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else if (eflag & FP_EX_OVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) eflag = FP_EX_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) else if (eflag & FP_EX_UNDERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) eflag = FP_EX_UNDERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else if (eflag & FP_EX_DIVZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) eflag = FP_EX_DIVZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else if (eflag & FP_EX_INEXACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) eflag = FP_EX_INEXACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Set CEXC, here is the rule:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * In general all FPU ops will set one and only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * bit in the CEXC field, this is always the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * when the IEEE exception trap is enabled in TEM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) fsr &= ~(FSR_CEXC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fsr |= ((long)eflag << FSR_CEXC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Set the AEXC field, rule is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * If a trap would not be generated, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * CEXC just generated is OR'd into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * existing value of AEXC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (would_trap == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) fsr |= ((long)eflag << FSR_AEXC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* If trapping, indicate fault trap type IEEE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (would_trap != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) fsr |= (1UL << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *pfsr = fsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return (would_trap ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u64 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u64 q[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) } *argp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Emulate the given insn, updating fsr and fregs appropriately. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* r is rd, b is rs2 and a is rs1. The *u arg tells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int freg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) argp rs1 = NULL, rs2 = NULL, rd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FP_DECL_EX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int IR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) long fsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #ifdef DEBUG_MATHEMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) printk("In do_mathemu(), emulating %08lx\n", insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch ((insn >> 5) & 0x1ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case FADDQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case FSUBQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case FMULQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case FQTOS: TYPE(3,1,1,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case FQTOD: TYPE(3,2,1,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case FITOQ: TYPE(3,3,1,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case FQTOI: TYPE(3,1,0,3,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case FADDD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case FSUBD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case FMULD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case FDIVD: TYPE(2,2,1,2,1,2,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case FADDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case FSUBS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case FMULS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case FDIVS: TYPE(2,1,1,1,1,1,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case FSMULD: TYPE(2,2,1,1,1,1,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case FDTOS: TYPE(2,1,1,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case FSTOD: TYPE(2,2,1,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case FSTOI: TYPE(2,1,0,1,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case FDTOI: TYPE(2,1,0,2,1,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case FITOS: TYPE(2,1,1,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case FITOD: TYPE(2,2,1,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case FMOVS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case FABSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case FNEGS: TYPE(2,1,0,1,0,0,0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch ((insn >> 5) & 0x1ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case FCMPS: TYPE(3,0,0,1,1,1,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case FCMPES: TYPE(3,0,0,1,1,1,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case FCMPD: TYPE(3,0,0,2,1,2,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case FCMPED: TYPE(3,0,0,2,1,2,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!type) { /* oops, didn't recognise that FPop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef DEBUG_MATHEMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) printk("attempt to emulate unrecognised FPop!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Decode the registers to be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) freg = (*pfsr >> 14) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *pfsr &= ~0x1c000; /* clear the traptype bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) freg = ((insn >> 14) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) switch (type & 0x3) { /* is rs1 single, double or quad? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (freg & 3) { /* quadwords must have bits 4&5 of the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* encoded reg. number set to zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *pfsr |= (6 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0; /* simulate invalid_fp_register exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (freg & 1) { /* doublewords must have bit 5 zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *pfsr |= (6 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rs1 = (argp)&fregs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) switch (type & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case 7: FP_UNPACK_QP (QA, rs1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 6: FP_UNPACK_DP (DA, rs1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case 5: FP_UNPACK_SP (SA, rs1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) freg = (insn & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch ((type >> 3) & 0x3) { /* same again for rs2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (freg & 3) { /* quadwords must have bits 4&5 of the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* encoded reg. number set to zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *pfsr |= (6 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0; /* simulate invalid_fp_register exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (freg & 1) { /* doublewords must have bit 5 zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *pfsr |= (6 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) rs2 = (argp)&fregs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) switch ((type >> 3) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case 7: FP_UNPACK_QP (QB, rs2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case 6: FP_UNPACK_DP (DB, rs2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case 5: FP_UNPACK_SP (SB, rs2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) freg = ((insn >> 25) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) switch ((type >> 6) & 0x3) { /* and finally rd. This one's a bit different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 0: /* dest is fcc. (this must be FCMPQ or FCMPEQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (freg) { /* V8 has only one set of condition codes, so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* anything but 0 in the rd field is an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *pfsr |= (6 << 14); /* (should probably flag as invalid opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0; /* but SIGFPE will do :-> ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (freg & 3) { /* quadwords must have bits 4&5 of the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* encoded reg. number set to zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *pfsr |= (6 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0; /* simulate invalid_fp_register exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (freg & 1) { /* doublewords must have bit 5 zeroed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *pfsr |= (6 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) rd = (void *)&fregs[freg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifdef DEBUG_MATHEMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) printk("executing insn...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* do the Right Thing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) switch ((insn >> 5) & 0x1ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* + */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case FADDS: FP_ADD_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case FADDD: FP_ADD_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case FADDQ: FP_ADD_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case FSUBS: FP_SUB_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case FSUBD: FP_SUB_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case FMULS: FP_MUL_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) FP_CONV (D, S, 2, 1, DB, SB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case FMULD: FP_MUL_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FP_CONV (Q, D, 4, 2, QB, DB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case FMULQ: FP_MUL_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* / */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case FDIVS: FP_DIV_S (SR, SA, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case FDIVD: FP_DIV_D (DR, DA, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* sqrt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case FSQRTS: FP_SQRT_S (SR, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case FSQRTD: FP_SQRT_D (DR, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case FSQRTQ: FP_SQRT_Q (QR, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* mov */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case FMOVS: rd->s = rs2->s; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case FABSS: rd->s = rs2->s & 0x7fffffff; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* float to int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* int to float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* float to float */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case FCMPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case FCMPES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) FP_CMP_S(IR, SB, SA, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IR == 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) (((insn >> 5) & 0x1ff) == FCMPES ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) FP_ISSIGNAN_S(SA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) FP_ISSIGNAN_S(SB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) FP_SET_EXCEPTION (FP_EX_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case FCMPD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case FCMPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) FP_CMP_D(IR, DB, DA, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (IR == 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (((insn >> 5) & 0x1ff) == FCMPED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) FP_ISSIGNAN_D(DA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) FP_ISSIGNAN_D(DB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) FP_SET_EXCEPTION (FP_EX_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case FCMPQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case FCMPEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FP_CMP_Q(IR, QB, QA, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (IR == 3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (((insn >> 5) & 0x1ff) == FCMPEQ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) FP_ISSIGNAN_Q(QA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) FP_ISSIGNAN_Q(QB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) FP_SET_EXCEPTION (FP_EX_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!FP_INHIBIT_RESULTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) switch ((type >> 6) & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case 0: fsr = *pfsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (IR == -1) IR = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* fcc is always fcc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fsr &= ~0xc00; fsr |= (IR << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *pfsr = fsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case 1: rd->s = IR; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case 5: FP_PACK_SP (rd, SR); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case 6: FP_PACK_DP (rd, DR); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case 7: FP_PACK_QP (rd, QR); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (_fex == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 1; /* success! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return record_exception(pfsr, _fex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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