Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* clear_page.S: UltraSparc optimized copy page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 1996, 1998, 1999, 2000, 2004 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1997 Jakub Jelinek (jakub@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/visasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	/* What we used to do was lock a TLB entry into a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	 * TLB slot, clear the page with interrupts disabled, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	 * restore the original TLB entry.  This was great for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	 * disturbing the TLB as little as possible, but it meant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	 * we had to keep interrupts disabled for a long time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	 * Now, we simply use the normal TLB loading mechanism,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	 * and this makes the cpu choose a slot all by itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	 * Then we do a normal TLB flush on exit.  We need only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	 * disable preemption during the clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	DCACHE_SIZE	(PAGE_SIZE * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #if (PAGE_SHIFT == 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PAGE_SIZE_REM	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #elif (PAGE_SHIFT == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PAGE_SIZE_REM	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #error Wrong PAGE_SHIFT specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	fsrc2	%reg0, %f48; 	fsrc2	%reg1, %f50;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	fsrc2	%reg2, %f52; 	fsrc2	%reg3, %f54;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	fsrc2	%reg4, %f56; 	fsrc2	%reg5, %f58;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	fsrc2	%reg6, %f60; 	fsrc2	%reg7, %f62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.align		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.globl		copy_user_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.type		copy_user_page,#function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	EXPORT_SYMBOL(copy_user_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) copy_user_page:		/* %o0=dest, %o1=src, %o2=vaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	lduw		[%g6 + TI_PRE_COUNT], %o4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	sethi		%hi(PAGE_OFFSET), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	sethi		%hi(PAGE_SIZE), %o3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ldx		[%g2 + %lo(PAGE_OFFSET)], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	sethi		%hi(PAGE_KERNEL_LOCKED), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ldx		[%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	sub		%o0, %g2, %g1		! dest paddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	sub		%o1, %g2, %g2		! src paddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	and		%o2, %o3, %o0		! vaddr D-cache alias bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	or		%g1, %g3, %g1		! dest TTE data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	or		%g2, %g3, %g2		! src TTE data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	sethi		%hi(TLBTEMP_BASE), %o3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	sethi		%hi(DCACHE_SIZE), %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	add		%o0, %o3, %o0		! dest TTE vaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	add		%o4, 1, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	add		%o0, %o1, %o1		! src TTE vaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* Disable preemption.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mov		TLB_TAG_ACCESS, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	stw		%o2, [%g6 + TI_PRE_COUNT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Load TLB entries.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	rdpr		%pstate, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	wrpr		%o2, PSTATE_IE, %pstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	stxa		%o0, [%g3] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	stxa		%g1, [%g0] ASI_DTLB_DATA_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	stxa		%o1, [%g3] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	stxa		%g2, [%g0] ASI_DTLB_DATA_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	wrpr		%o2, 0x0, %pstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) cheetah_copy_page_insn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ba,pt		%xcc, 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	VISEntryHalf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	membar		#StoreLoad | #StoreStore | #LoadStore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	sethi		%hi((PAGE_SIZE/64)-2), %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mov		%o0, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	prefetch	[%o1 + 0x000], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	or		%o2, %lo((PAGE_SIZE/64)-2), %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	prefetch	[%o1 + 0x040], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	prefetch	[%o1 + 0x080], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	prefetch	[%o1 + 0x0c0], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ldd		[%o1 + 0x000], %f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	prefetch	[%o1 + 0x100], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ldd		[%o1 + 0x008], %f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	prefetch	[%o1 + 0x140], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ldd		[%o1 + 0x010], %f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	prefetch	[%o1 + 0x180], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	fsrc2		%f0, %f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ldd		[%o1 + 0x018], %f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	fsrc2		%f2, %f18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ldd		[%o1 + 0x020], %f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	fsrc2		%f4, %f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ldd		[%o1 + 0x028], %f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	fsrc2		%f6, %f22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ldd		[%o1 + 0x030], %f12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	fsrc2		%f8, %f24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ldd		[%o1 + 0x038], %f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	fsrc2		%f10, %f26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ldd		[%o1 + 0x040], %f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 1:	ldd		[%o1 + 0x048], %f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	fsrc2		%f12, %f28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ldd		[%o1 + 0x050], %f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	fsrc2		%f14, %f30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	stda		%f16, [%o0] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ldd		[%o1 + 0x058], %f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	fsrc2		%f0, %f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ldd		[%o1 + 0x060], %f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	fsrc2		%f2, %f18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ldd		[%o1 + 0x068], %f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	fsrc2		%f4, %f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ldd		[%o1 + 0x070], %f12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	fsrc2		%f6, %f22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ldd		[%o1 + 0x078], %f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	fsrc2		%f8, %f24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ldd		[%o1 + 0x080], %f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	prefetch	[%o1 + 0x180], #one_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	fsrc2		%f10, %f26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	subcc		%o2, 1, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	bne,pt		%xcc, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ldd		[%o1 + 0x048], %f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	fsrc2		%f12, %f28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ldd		[%o1 + 0x050], %f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	fsrc2		%f14, %f30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	stda		%f16, [%o0] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ldd		[%o1 + 0x058], %f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	fsrc2		%f0, %f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ldd		[%o1 + 0x060], %f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	fsrc2		%f2, %f18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ldd		[%o1 + 0x068], %f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	fsrc2		%f4, %f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ldd		[%o1 + 0x070], %f12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	fsrc2		%f6, %f22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ldd		[%o1 + 0x078], %f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	fsrc2		%f8, %f24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	fsrc2		%f10, %f26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	fsrc2		%f12, %f28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	fsrc2		%f14, %f30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	stda		%f16, [%o0] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	VISExitHalf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ba,pt		%xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	VISEntry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ldub		[%g6 + TI_FAULT_CODE], %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	mov		%o0, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	cmp		%g3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	rd		%asi, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	be,a,pt		%icc, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 wr		%g0, ASI_BLK_P, %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	wr		%g0, ASI_BLK_COMMIT_P, %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 1:	ldda		[%o1] ASI_BLK_P, %f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ldda		[%o1] ASI_BLK_P, %f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	sethi		%hi(PAGE_SIZE), %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 1:	TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ldda		[%o1] ASI_BLK_P, %f32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	stda		%f48, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	sub		%o2, 0x40, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ldda		[%o1] ASI_BLK_P, %f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	stda		%f48, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	sub		%o2, 0x40, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	TOUCH(f32, f34, f36, f38, f40, f42, f44, f46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ldda		[%o1] ASI_BLK_P, %f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	stda		%f48, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	sub		%o2, 0x40, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	cmp		%o2, PAGE_SIZE_REM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	bne,pt		%xcc, 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #if (PAGE_SHIFT == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ldda		[%o1] ASI_BLK_P, %f32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	stda		%f48, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	sub		%o2, 0x40, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ldda		[%o1] ASI_BLK_P, %f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	stda		%f48, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	add		%o1, 0x40, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	sub		%o2, 0x40, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	stda		%f32, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	stda		%f0, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	stda		%f0, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	add		%o0, 0x40, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	stda		%f16, [%o0] %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	wr		%g3, 0x0, %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	VISExit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	stxa		%g0, [%g1] ASI_DMMU_DEMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	sethi		%hi(DCACHE_SIZE), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	stxa		%g0, [%g1 + %g2] ASI_DMMU_DEMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	retl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 stw		%o4, [%g6 + TI_PRE_COUNT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.size		copy_user_page, .-copy_user_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.globl		cheetah_patch_copy_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cheetah_patch_copy_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	sethi		%hi(0x01000000), %o1	! NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	sethi		%hi(cheetah_copy_page_insn), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	or		%o0, %lo(cheetah_copy_page_insn), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	stw		%o1, [%o0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	membar		#StoreStore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	flush		%o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	retl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 nop