Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * VISsave.S: Code for saving FPU register state for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *            VIS routines. One should not call this directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *            but use macros provided in <asm/visasm.h>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/visasm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	/* On entry: %o5=current FPRS value, %g7 is callers address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	/* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	/* Nothing special need be done here to handle pre-emption, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	 * FPU save/restore mechanism is already preemption safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	.align		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ENTRY(VISenter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	ldub		[%g6 + TI_FPDEPTH], %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	brnz,a,pn	%g1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 cmp		%g1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	stb		%g0, [%g6 + TI_FPSAVED]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	stx		%fsr, [%g6 + TI_XFSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 9:	jmpl		%g7 + %g0, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 1:	bne,pn		%icc, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 srl		%g1, 1, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) vis1:	ldub		[%g6 + TI_FPSAVED], %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	stx		%fsr, [%g6 + TI_XFSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	or		%g3, %o5, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	stb		%g3, [%g6 + TI_FPSAVED]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	rd		%gsr, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clr		%g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	ba,pt		%xcc, 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	 stx		%g3, [%g6 + TI_GSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 2:	add		%g6, %g1, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mov		FPRS_DU | FPRS_DL | FPRS_FEF, %o5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	sll		%g1, 3, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	stb		%o5, [%g3 + TI_FPSAVED]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	rd		%gsr, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	add		%g6, %g1, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	stx		%g2, [%g3 + TI_GSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	add		%g6, %g1, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	stx		%fsr, [%g2 + TI_XFSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	sll		%g1, 5, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 3:	andcc		%o5, FPRS_DL|FPRS_DU, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	be,pn		%icc, 9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	 add		%g6, TI_FPREGS, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	andcc		%o5, FPRS_DL, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	be,pn		%icc, 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	 add		%g6, TI_FPREGS+0x40, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	stda		%f0, [%g2 + %g1] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	stda		%f16, [%g3 + %g1] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	andcc		%o5, FPRS_DU, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	be,pn		%icc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 4:	 add		%g1, 128, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	stda		%f32, [%g2 + %g1] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	stda		%f48, [%g3 + %g1] ASI_BLK_P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 5:	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	ba,pt		%xcc, 80f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	.align		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 80:	jmpl		%g7 + %g0, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ENDPROC(VISenter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) EXPORT_SYMBOL(VISenter)