Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * trampoline.S: SMP cpu boot-up trampoline code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/psr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/vaddrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/contregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	.globl sun4m_cpu_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	.globl sun4d_cpu_startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	.align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* When we start up a cpu for the first time it enters this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * This initializes the chip from whatever state the prom left it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * in and sets PIL in %psr to 15, no irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) sun4m_cpu_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) cpu1_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	sethi	%hi(trapbase_cpu1), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	b	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	 or	%g3, %lo(trapbase_cpu1), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) cpu2_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	sethi	%hi(trapbase_cpu2), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	b	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	 or	%g3, %lo(trapbase_cpu2), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) cpu3_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	sethi	%hi(trapbase_cpu3), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	b	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	 or	%g3, %lo(trapbase_cpu3), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	set	(PSR_PIL | PSR_S | PSR_PS), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	wr	%g1, 0x0, %psr		! traps off though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* Our %wim is one behind CWP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	mov	2, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	wr	%g1, 0x0, %wim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* This identifies "this cpu". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	wr	%g3, 0x0, %tbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* Give ourselves a stack and curptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	set	current_set, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	srl	%g3, 10, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	and	%g4, 0xc, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ld	[%g5 + %g4], %g6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	add	%g6, %sp, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* Turn on traps (PSR_ET). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	rd	%psr, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	wr	%g1, PSR_ET, %psr	! traps on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* Init our caches, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	set	poke_srmmu, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ld	[%g5], %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	call	%g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Start this processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	call	smp_callin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	b,a	smp_panic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) smp_panic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	call	cpu_panic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* CPUID in bootbus can be found at PA 0xff0140000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SUN4D_BOOTBUS_CPUID	0xf0140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) sun4d_cpu_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	set	(PSR_PIL | PSR_S | PSR_PS), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	wr	%g1, 0x0, %psr		! traps off though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Our %wim is one behind CWP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	mov	2, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	wr	%g1, 0x0, %wim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Set tbr - we use just one trap table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	set	trapbase, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	wr	%g1, 0x0, %tbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* Get our CPU id out of bootbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	set	SUN4D_BOOTBUS_CPUID, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	lduba	[%g3] ASI_M_CTL, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	and	%g3, 0xf8, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	srl	%g3, 3, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	sta	%g1, [%g0] ASI_M_VIKING_TMP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Give ourselves a stack and curptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	set	current_set, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	srl	%g3, 1, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ld	[%g5 + %g4], %g6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	add	%g6, %sp, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* Turn on traps (PSR_ET). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	rd	%psr, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	wr	%g1, PSR_ET, %psr	! traps on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* Init our caches, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	set	poke_srmmu, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ld	[%g5], %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	call	%g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Start this processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	call	smp_callin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	b,a	smp_panic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)         .global leon_smp_cpu_startup, smp_penguin_ctable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) leon_smp_cpu_startup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)         set smp_penguin_ctable,%g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)         ld [%g1+4],%g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)         srl %g1,4,%g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)         set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	sta %g1, [%g5] ASI_LEON_MMUREGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	set	(PSR_PIL | PSR_S | PSR_PS), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	wr	%g1, 0x0, %psr		! traps off though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* Our %wim is one behind CWP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	mov	2, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	wr	%g1, 0x0, %wim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* Set tbr - we use just one trap table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	set	trapbase, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	wr	%g1, 0x0, %tbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* Get our CPU id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)         rd     %asr17,%g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* Give ourselves a stack and curptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	set	current_set, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	srl	%g3, 28, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	sll	%g4, 2, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ld	[%g5 + %g4], %g6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	sethi	%hi(THREAD_SIZE - STACKFRAME_SZ), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	or	%sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	add	%g6, %sp, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Turn on traps (PSR_ET). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	rd	%psr, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	wr	%g1, PSR_ET, %psr	! traps on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	WRITE_PAUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Init our caches, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	set	poke_srmmu, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	ld	[%g5], %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	call	%g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Start this processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	call	smp_callin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	b,a	smp_panic