^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* linux/arch/sparc/kernel/time.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Chris Davis (cdavis@cois.on.ca) 03/27/1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Added support for the intersil on the sun4/4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Support for MicroSPARC-IIep, PCI CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file handles the Sparc specific time handling details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * "A Kernel Model for Precision Timekeeping" by Dave Mills
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rtc/m48t59.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/profile.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/mc146818rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/idprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/pcic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/irq_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static __volatile__ u64 timer_cs_internal_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static char timer_cs_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct clock_event_device timer_ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static char timer_ce_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_SPINLOCK(rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) EXPORT_SYMBOL(rtc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long profile_pc(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern char __copy_user_begin[], __copy_user_end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern char __bzero_begin[], __bzero_end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long pc = regs->pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (in_lock_functions(pc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (pc >= (unsigned long) __copy_user_begin &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pc < (unsigned long) __copy_user_end) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (pc >= (unsigned long) __bzero_begin &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pc < (unsigned long) __bzero_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pc = regs->u_regs[UREG_RETPC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) EXPORT_SYMBOL(profile_pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) volatile u32 __iomem *master_l10_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (timer_cs_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) write_seqlock(&timer_cs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) timer_cs_internal_counter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sparc_config.clear_clock_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) write_sequnlock(&timer_cs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sparc_config.clear_clock_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (timer_ce_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) timer_ce.event_handler(&timer_ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int timer_ce_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) timer_ce_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) smp_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int timer_ce_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) timer_ce_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) smp_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static __init void setup_timer_ce(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clock_event_device *ce = &timer_ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BUG_ON(smp_processor_id() != boot_cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ce->name = "timer_ce";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ce->rating = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ce->features = CLOCK_EVT_FEAT_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ce->set_state_shutdown = timer_ce_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ce->set_state_periodic = timer_ce_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ce->tick_resume = timer_ce_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ce->cpumask = cpu_possible_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ce->shift = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ce->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clockevents_register_device(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static unsigned int sbus_cycles_offset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 val, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val = sbus_readl(master_l10_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Limit hit? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (val & TIMER_LIMIT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) offset += sparc_config.cs_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u64 timer_cs_read(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int seq, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u64 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) seq = read_seqbegin(&timer_cs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cycles = timer_cs_internal_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) offset = sparc_config.get_cycles_offset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } while (read_seqretry(&timer_cs_lock, seq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Count absolute cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cycles *= sparc_config.cs_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cycles += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct clocksource timer_cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "timer_cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .rating = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .read = timer_cs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .mask = CLOCKSOURCE_MASK(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static __init int setup_timer_cs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) timer_cs_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int percpu_ce_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int cpu = cpumask_first(evt->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sparc_config.load_profile_irq(cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int percpu_ce_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int cpu = cpumask_first(evt->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sparc_config.load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int percpu_ce_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int cpu = cpumask_first(evt->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int next = (unsigned int)delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) sparc_config.load_profile_irq(cpu, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void register_percpu_ce(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (sparc_config.features & FEAT_L14_ONESHOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) features |= CLOCK_EVT_FEAT_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ce->name = "percpu_ce";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ce->rating = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ce->features = features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ce->set_state_shutdown = percpu_ce_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ce->set_state_periodic = percpu_ce_set_periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ce->set_state_oneshot = percpu_ce_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ce->set_next_event = percpu_ce_set_next_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ce->cpumask = cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ce->shift = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ce->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ce->max_delta_ticks = (unsigned long)sparc_config.clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ce->min_delta_ns = clockevent_delta2ns(100, ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ce->min_delta_ticks = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clockevents_register_device(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct m48t59_plat_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return readb(pdata->ioaddr + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct m48t59_plat_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writeb(val, pdata->ioaddr + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct m48t59_plat_data m48t59_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .read_byte = mostek_read_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .write_byte = mostek_write_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* resource is set at runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct platform_device m48t59_rtc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .name = "rtc-m48t59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .platform_data = &m48t59_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int clock_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const char *model = of_get_property(dp, "model", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Only the primary RTC has an address property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!of_find_property(dp, "address", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) m48t59_rtc.resource = &op->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!strcmp(model, "mk48t02")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Map the clock register io area read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 2048, "rtc-m48t59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) m48t59_data.type = M48T59RTC_TYPE_M48T02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else if (!strcmp(model, "mk48t08")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 8192, "rtc-m48t59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) m48t59_data.type = M48T59RTC_TYPE_M48T08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (platform_device_register(&m48t59_rtc) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) printk(KERN_ERR "Registering RTC device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct of_device_id clock_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct platform_driver clock_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .probe = clock_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .of_match_table = clock_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Probe for the mostek real time clock chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int __init clock_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return platform_driver_register(&clock_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Must be after subsys_initcall() so that busses are probed. Must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * be before device_initcall() because things like the RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * need to see the clock registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) fs_initcall(clock_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void __init sparc32_late_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (sparc_config.features & FEAT_L10_CLOCKEVENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) setup_timer_ce();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) setup_timer_cs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) register_percpu_ce(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void __init sbus_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sparc_config.get_cycles_offset = sbus_cycles_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sparc_config.init_timers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void __init time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sparc_config.features = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) late_time_init = sparc32_late_time_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (pcic_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pci_time_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) sbus_time_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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