Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* sysfs.c: Topology sysfs support code for sparc64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007 David S. Miller <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cpudata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/hypervisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static DEFINE_PER_CPU(struct hv_mmu_statistics, mmu_stats) __attribute__((aligned(64)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SHOW_MMUSTAT_ULONG(NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static ssize_t show_##NAME(struct device *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 			struct device_attribute *attr, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct hv_mmu_statistics *p = &per_cpu(mmu_stats, dev->id); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	return sprintf(buf, "%lu\n", p->NAME); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static DEVICE_ATTR(NAME, 0444, show_##NAME, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctxnon0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctxnon0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctx0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctx0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_8k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_64k_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_4mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_256mb_tte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static struct attribute *mmu_stat_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	&dev_attr_immu_tsb_hits_ctx0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	&dev_attr_immu_tsb_ticks_ctx0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	&dev_attr_immu_tsb_hits_ctx0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	&dev_attr_immu_tsb_ticks_ctx0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	&dev_attr_immu_tsb_hits_ctx0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	&dev_attr_immu_tsb_ticks_ctx0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	&dev_attr_immu_tsb_hits_ctx0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	&dev_attr_immu_tsb_ticks_ctx0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	&dev_attr_immu_tsb_hits_ctxnon0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	&dev_attr_immu_tsb_ticks_ctxnon0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	&dev_attr_immu_tsb_hits_ctxnon0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	&dev_attr_immu_tsb_ticks_ctxnon0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	&dev_attr_immu_tsb_hits_ctxnon0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	&dev_attr_immu_tsb_ticks_ctxnon0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	&dev_attr_immu_tsb_hits_ctxnon0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	&dev_attr_immu_tsb_ticks_ctxnon0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	&dev_attr_dmmu_tsb_hits_ctx0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	&dev_attr_dmmu_tsb_ticks_ctx0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	&dev_attr_dmmu_tsb_hits_ctx0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	&dev_attr_dmmu_tsb_ticks_ctx0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	&dev_attr_dmmu_tsb_hits_ctx0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	&dev_attr_dmmu_tsb_ticks_ctx0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	&dev_attr_dmmu_tsb_hits_ctx0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	&dev_attr_dmmu_tsb_ticks_ctx0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	&dev_attr_dmmu_tsb_hits_ctxnon0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	&dev_attr_dmmu_tsb_ticks_ctxnon0_8k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	&dev_attr_dmmu_tsb_hits_ctxnon0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	&dev_attr_dmmu_tsb_ticks_ctxnon0_64k_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	&dev_attr_dmmu_tsb_hits_ctxnon0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	&dev_attr_dmmu_tsb_ticks_ctxnon0_4mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	&dev_attr_dmmu_tsb_hits_ctxnon0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	&dev_attr_dmmu_tsb_ticks_ctxnon0_256mb_tte.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static struct attribute_group mmu_stat_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.attrs = mmu_stat_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.name = "mmu_stats",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static long read_mmustat_enable(void *data __maybe_unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned long ra = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	sun4v_mmustat_info(&ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return ra != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static long write_mmustat_enable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	unsigned long ra, orig_ra, *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (*val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		ra = __pa(&per_cpu(mmu_stats, smp_processor_id()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		ra = 0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return sun4v_mmustat_conf(ra, &orig_ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static ssize_t show_mmustat_enable(struct device *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	long val = work_on_cpu(s->id, read_mmustat_enable, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return sprintf(buf, "%lx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static ssize_t store_mmustat_enable(struct device *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	long err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ret = sscanf(buf, "%lu", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	err = work_on_cpu(s->id, write_mmustat_enable, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static DEVICE_ATTR(mmustat_enable, 0644, show_mmustat_enable, store_mmustat_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int mmu_stats_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int register_mmu_stats(struct device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!mmu_stats_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	device_create_file(s, &dev_attr_mmustat_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	return sysfs_create_group(&s->kobj, &mmu_stat_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void unregister_mmu_stats(struct device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (!mmu_stats_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	sysfs_remove_group(&s->kobj, &mmu_stat_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	device_remove_file(s, &dev_attr_mmustat_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SHOW_CPUDATA_ULONG_NAME(NAME, MEMBER) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static ssize_t show_##NAME(struct device *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		struct device_attribute *attr, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	cpuinfo_sparc *c = &cpu_data(dev->id); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return sprintf(buf, "%lu\n", c->MEMBER); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SHOW_CPUDATA_UINT_NAME(NAME, MEMBER) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static ssize_t show_##NAME(struct device *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		struct device_attribute *attr, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	cpuinfo_sparc *c = &cpu_data(dev->id); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return sprintf(buf, "%u\n", c->MEMBER); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SHOW_CPUDATA_ULONG_NAME(clock_tick, clock_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SHOW_CPUDATA_UINT_NAME(l1_dcache_size, dcache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SHOW_CPUDATA_UINT_NAME(l1_dcache_line_size, dcache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SHOW_CPUDATA_UINT_NAME(l1_icache_size, icache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SHOW_CPUDATA_UINT_NAME(l1_icache_line_size, icache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SHOW_CPUDATA_UINT_NAME(l2_cache_size, ecache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SHOW_CPUDATA_UINT_NAME(l2_cache_line_size, ecache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct device_attribute cpu_core_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__ATTR(clock_tick,          0444, show_clock_tick, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	__ATTR(l1_dcache_size,      0444, show_l1_dcache_size, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	__ATTR(l1_dcache_line_size, 0444, show_l1_dcache_line_size, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	__ATTR(l1_icache_size,      0444, show_l1_icache_size, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	__ATTR(l1_icache_line_size, 0444, show_l1_icache_line_size, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	__ATTR(l2_cache_size,       0444, show_l2_cache_size, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	__ATTR(l2_cache_line_size,  0444, show_l2_cache_line_size, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static DEFINE_PER_CPU(struct cpu, cpu_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int register_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct cpu *c = &per_cpu(cpu_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct device *s = &c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	for (i = 0; i < ARRAY_SIZE(cpu_core_attrs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		device_create_file(s, &cpu_core_attrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	register_mmu_stats(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int unregister_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct cpu *c = &per_cpu(cpu_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct device *s = &c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	unregister_mmu_stats(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	for (i = 0; i < ARRAY_SIZE(cpu_core_attrs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		device_remove_file(s, &cpu_core_attrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void __init check_mmu_stats(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	unsigned long dummy1, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (tlb_type != hypervisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	err = sun4v_mmustat_info(&dummy1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		mmu_stats_supported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void register_nodes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	for (i = 0; i < MAX_NUMNODES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		register_one_node(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int __init topology_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	register_nodes();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	check_mmu_stats();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		struct cpu *c = &per_cpu(cpu_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		register_cpu(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "sparc/topology:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				register_cpu_online, unregister_cpu_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	WARN_ON(ret < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) subsys_initcall(topology_init);