^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sun4m SMP support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/profile.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/switch_to.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IRQ_IPI_SINGLE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IRQ_IPI_MASK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IRQ_IPI_RESCHED 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IRQ_CROSS_CALL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) swap_ulong(volatile unsigned long *ptr, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __asm__ __volatile__("swap [%1], %0\n\t" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "=&r" (val), "=&r" (ptr) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "0" (val), "1" (ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void sun4m_cpu_pre_starting(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void sun4m_cpu_pre_online(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int cpuid = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Allow master to continue. The master will then give us the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * go-ahead by setting the smp_commenced_mask and will wait without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * timeouts until our setup is completed fully (signified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * our bit being set in the cpu_online_mask).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) swap_ulong(&cpu_callin_map[cpuid], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* XXX: What's up with all the flushes? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) local_ops->tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Fix idle thread fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __asm__ __volatile__("ld [%0], %%g6\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) : : "r" (¤t_set[cpuid])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) : "memory" /* paranoid */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Attach to the address space of init_task. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mmgrab(&init_mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) current->active_mm = &init_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Cycle through the processors asking the PROM to start each one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __init smp4m_boot_cpus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) sun4m_unmask_profile_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int smp4m_boot_one_cpu(int i, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long *entry = &sun4m_cpu_startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int cpu_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cpu_find_by_mid(i, &cpu_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) current_set[i] = task_thread_info(idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* See trampoline.S for details... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) entry += ((i - 1) * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Initialize the contexts table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Since the call to prom_startcpu() trashes the structure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * we need to re-initialize it for each cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) smp_penguin_ctable.which_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) smp_penguin_ctable.reg_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* whirrr, whirrr, whirrrrrrrrr... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* wheee... it's going... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (timeout = 0; timeout < 10000; timeout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (cpu_callin_map[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!(cpu_callin_map[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) printk(KERN_ERR "Processor %d is stuck.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __init smp4m_smp_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int i, first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* setup cpu list for irq rotation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) prev = &first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for_each_online_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *prev = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) prev = &cpu_data(i).next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *prev = first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Ok, they are spinning and ready to go. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void sun4m_send_ipi(int cpu, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void sun4m_ipi_resched(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void sun4m_ipi_single(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void sun4m_ipi_mask_one(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sun4m_send_ipi(cpu, IRQ_IPI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct smp_funcall {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) smpfunc_t func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long arg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long arg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long arg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } ccall_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static DEFINE_SPINLOCK(cross_call_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Cross calls must be serialized, at least currently. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long arg2, unsigned long arg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long arg4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) register int ncpus = SUN4M_NCPUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_lock_irqsave(&cross_call_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Init function glue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ccall_info.func = func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ccall_info.arg1 = arg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ccall_info.arg2 = arg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ccall_info.arg3 = arg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ccall_info.arg4 = arg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ccall_info.arg5 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Init receive/complete mapping, plus fire the IPI's off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) register int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cpumask_clear_cpu(smp_processor_id(), &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cpumask_and(&mask, cpu_online_mask, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (i = 0; i < ncpus; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (cpumask_test_cpu(i, &mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ccall_info.processors_in[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ccall_info.processors_out[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sun4m_send_ipi(i, IRQ_CROSS_CALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ccall_info.processors_in[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ccall_info.processors_out[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) register int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!cpumask_test_cpu(i, &mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) while (!ccall_info.processors_in[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } while (++i < ncpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!cpumask_test_cpu(i, &mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) while (!ccall_info.processors_out[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } while (++i < ncpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spin_unlock_irqrestore(&cross_call_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Running cross calls. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void smp4m_cross_call_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int i = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ccall_info.processors_in[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ccall_info.arg4, ccall_info.arg5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ccall_info.processors_out[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct pt_regs *old_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct clock_event_device *ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ce = &per_cpu(sparc32_clockevent, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (clockevent_state_periodic(ce))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sun4m_clear_profile_irq(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ce->event_handler(ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct sparc32_ipi_ops sun4m_ipi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cross_call = sun4m_cross_call,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .resched = sun4m_ipi_resched,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .single = sun4m_ipi_single,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .mask_one = sun4m_ipi_mask_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) void __init sun4m_init_smp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sparc32_ipi_ops = &sun4m_ipi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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