^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sun4m irq support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * djhr: Hacked out of irq.c into a CPU dependent version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched/debug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Sample sun4m IRQ layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 0x22 - Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0x24 - ESP SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 0x26 - Lance ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 0x2b - Floppy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 0x2c - Zilog uart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 0x32 - SBUS level 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 0x33 - Parallel port, SBUS level 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 0x35 - SBUS level 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 0x37 - SBUS level 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 0x39 - Audio, Graphics card, SBUS level 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 0x3b - SBUS level 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 0x3d - SBUS level 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Each interrupt source has a mask bit in the interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * When the mask bit is set, this blocks interrupt deliver. So you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * clear the bit to enable the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Interrupts numbered less than 0x10 are software triggered interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * and unused by Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Interrupt level assignment on sun4m:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * level source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * ------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 1 softint-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 2 softint-2, VME/SBUS level 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 3 softint-3, VME/SBUS level 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 4 softint-4, onboard SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 5 softint-5, VME/SBUS level 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 6 softint-6, onboard ETHERNET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 7 softint-7, VME/SBUS level 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 8 softint-8, onboard VIDEO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 9 softint-9, VME/SBUS level 5, Module Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 10 softint-10, system counter/timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 11 softint-11, VME/SBUS level 6, Floppy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 12 softint-12, Keyboard/Mouse, Serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 13 softint-13, VME/SBUS level 7, ISDN Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 14 softint-14, per-processor counter/timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 15 softint-15, Asynchronous Errors (broadcast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Each interrupt source is masked distinctly in the sun4m interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * registers. The PIL level alone is therefore ambiguous, since multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * interrupt sources map to a single PIL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * This ambiguity is resolved in the 'intr' property for device nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * in the OF device tree. Each 'intr' property entry is composed of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * two 32-bit words. The first word is the IRQ priority value, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * is what we're intersted in. The second word is the IRQ vector, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * is unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * The low 4 bits of the IRQ priority indicate the PIL, and the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * whereas a value of 0x33 is SBUS level 2. Here are some sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Tadpole S3 GX systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * esp: 0x24 onboard ESP SCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * le: 0x26 onboard Lance ETHERNET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * p9100: 0x32 SBUS level 1 P9100 video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * bpp: 0x33 SBUS level 2 BPP parallel port device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * SUNW,leo: 0x39 SBUS level 5 LEO video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * pcmcia: 0x3b SBUS level 6 PCMCIA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * uctrl: 0x3b SBUS level 6 UCTRL device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * modem: 0x3d SBUS level 7 MODEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * zs: 0x2c onboard keyboard/mouse/serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * floppy: 0x2b onboard Floppy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * power: 0x22 onboard power device (XXX unknown mask bit XXX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Code in entry.S needs to get at these register mappings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct sun4m_irq_global __iomem *sun4m_irq_global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct sun4m_handler_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool percpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Dave Redman (djhr@tadpole.co.uk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * The sun4m interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SUN4M_INT_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SUN4M_INT_E14 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SUN4M_INT_E10 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SUN4M_INT_REALTIME 0x00080000 /* system timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SUN4M_INT_M2S_WRITE_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SUN4M_INT_ECC_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SUN4M_INT_VME_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SUN4M_INT_SBUS(x) (1 << (x+7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SUN4M_INT_VME(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Interrupt levels used by OBP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OBP_INT_LEVEL_SOFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OBP_INT_LEVEL_ONBOARD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OBP_INT_LEVEL_SBUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OBP_INT_LEVEL_VME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned long sun4m_imask[0x50] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* 0x00 - SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0, SUN4M_SOFT_INT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 0x10 - soft */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0, SUN4M_SOFT_INT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* 0x20 - onboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 0x30 - sbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0, SUN4M_INT_SBUS(6), 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* 0x40 - vme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0, SUN4M_INT_VME(6), 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void sun4m_mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct sun4m_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (handler_data->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (handler_data->percpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void sun4m_unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct sun4m_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (handler_data->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (handler_data->percpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static unsigned int sun4m_startup_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) irq_link(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sun4m_unmask_irq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void sun4m_shutdown_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sun4m_mask_irq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) irq_unlink(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct irq_chip sun4m_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "sun4m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .irq_startup = sun4m_startup_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .irq_shutdown = sun4m_shutdown_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .irq_mask = sun4m_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .irq_unmask = sun4m_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static unsigned int sun4m_build_device_irq(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int real_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct sun4m_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int pil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (real_irq >= OBP_INT_LEVEL_VME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) prom_printf("Bogus sun4m IRQ %u\n", real_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pil = (real_irq & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) irq = irq_alloc(real_irq, pil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (irq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) handler_data = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (unlikely(handler_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (unlikely(!handler_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) handler_data->mask = sun4m_imask[real_irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) irq_set_chip_and_handler_name(irq, &sun4m_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) handle_level_irq, "level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) irq_set_handler_data(irq, handler_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct sun4m_timer_percpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 l14_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 l14_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 l14_limit_noclear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 user_timer_start_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct sun4m_timer_global {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 l10_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 l10_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 l10_limit_noclear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 timer_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct sun4m_timer_global __iomem *timers_global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void sun4m_clear_clock_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sbus_readl(&timers_global->l10_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void sun4m_nmi(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned long afsr, afar, si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) printk(KERN_ERR "Aieee: sun4m NMI received!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* XXX HyperSparc hack XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __asm__ __volatile__("mov 0x500, %%g1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "lda [%%g1] 0x4, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "mov 0x600, %%g1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "lda [%%g1] 0x4, %1\n\t" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "=r" (afsr), "=r" (afar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) si = sbus_readl(&sun4m_irq_global->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) printk(KERN_ERR "si=%08lx\n", si);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (si & SUN4M_INT_MODULE_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) printk(KERN_ERR "Module async error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (si & SUN4M_INT_M2S_WRITE_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) printk(KERN_ERR "MBus/SBus async error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (si & SUN4M_INT_ECC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) printk(KERN_ERR "ECC memory error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (si & SUN4M_INT_VME_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) printk(KERN_ERR "VME async error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) printk(KERN_ERR "you lose buddy boy...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) show_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void sun4m_unmask_profile_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void sun4m_clear_profile_irq(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sbus_readl(&timers_percpu[cpu]->l14_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void sun4m_load_profile_irq(int cpu, unsigned int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int value = limit ? timer_value(limit) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sbus_writel(value, &timers_percpu[cpu]->l14_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void __init sun4m_init_timers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device_node *dp = of_find_node_by_name(NULL, "counter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int i, err, len, num_cpu_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const u32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!dp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) addr = of_get_property(dp, "address", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) of_node_put(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) num_cpu_timers = (len / sizeof(u32)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (i = 0; i < num_cpu_timers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) timers_percpu[i] = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (unsigned long) addr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) timers_global = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) (unsigned long) addr[num_cpu_timers];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Every per-cpu timer works in timer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sbus_writel(0x00000000, &timers_global->timer_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sparc_config.features |= FEAT_L14_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sparc_config.features |= FEAT_L10_CLOCKEVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sparc_config.features |= FEAT_L10_CLOCKSOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sbus_writel(timer_value(sparc_config.cs_period),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) &timers_global->l10_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) master_l10_counter = &timers_global->l10_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < num_cpu_timers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sbus_writel(0, &timers_percpu[i]->l14_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (num_cpu_timers == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* For SMP we use the level 14 ticker, however the bootup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * has copied the firmware's level 14 vector into the boot cpu's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * trap table, we must fix this now or we get squashed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) trap_table->inst_one = lvl14_save[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) trap_table->inst_two = lvl14_save[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) trap_table->inst_three = lvl14_save[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) trap_table->inst_four = lvl14_save[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void __init sun4m_init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int len, i, mid, num_cpu_iregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const u32 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!dp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) addr = of_get_property(dp, "address", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) of_node_put(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) num_cpu_iregs = (len / sizeof(u32)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = 0; i < num_cpu_iregs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sun4m_irq_percpu[i] = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (unsigned long) addr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) sun4m_irq_global = (void __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (unsigned long) addr[num_cpu_iregs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (num_cpu_iregs == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sbus_writel(0, &sun4m_irq_global->interrupt_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sparc_config.init_timers = sun4m_init_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sparc_config.build_device_irq = sun4m_build_device_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sparc_config.clock_rate = SBUS_CLOCK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sparc_config.clear_clock_irq = sun4m_clear_clock_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sparc_config.load_profile_irq = sun4m_load_profile_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Cannot enable interrupts until OBP ticker is disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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