^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SS1000/SC2000 interrupt handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Heavily based on arch/sparc/kernel/irq.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/sbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Sun4d interrupts fall roughly into two categories. SBUS and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * cpu local. CPU local interrupts cover the timer interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * and whatnot, and we encode those as normal PILs between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 0 and 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * SBUS interrupts are encodes as a combination of board, level and slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct sun4d_handler_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int cpuid; /* target cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int real_irq; /* interrupt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned int sun4d_encode_irq(int board, int lvl, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return (board + 1) << 5 | (lvl << 2) | slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct sun4d_timer_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 l10_timer_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 l10_cur_countx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 l10_limit_noclear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 l10_cur_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct sun4d_timer_regs __iomem *sun4d_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN4D_TIMER_IRQ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Specify which cpu handle interrupts from which board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Index is board - value is cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static unsigned char board_to_cpu[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int pil_to_sbus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Exported for sun4d_smp.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE_SPINLOCK(sun4d_imsk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* SBUS interrupts are encoded integers including the board number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * (plus one), the SBUS level, and the SBUS slot number. Sun4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * IRQ dispatch is done by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 1) Reading the BW local interrupt table in order to get the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * interrupt mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * This table is indexed by SBUS interrupt level which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * derived from the PIL we got interrupted on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 2) For each bus showing interrupt pending from #1, read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * SBI interrupt state register. This will indicate which slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * have interrupts pending for that SBUS interrupt level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 3) Call the genreric IRQ support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void sun4d_sbus_handler_irq(int sbusl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int bus_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int sbino, slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int sbil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bw_clear_intr_mask(sbusl, bus_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sbil = (sbusl << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Loop for each pending SBI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int idx, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!(bus_mask & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* XXX This seems to ACK the irq twice. acquire_sbi()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * XXX uses swap, therefore this writes 0xf << sbil,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * XXX then later release_sbi() will write the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * XXX bits which were set again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mask &= (0xf << sbil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Loop for each pending SBI slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) slot = (1 << sbil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (idx = 0; mask != 0; idx++, slot <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int pil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct irq_bucket *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (!(mask & slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mask &= ~slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pil = sun4d_encode_irq(sbino, sbusl, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) p = irq_map[pil];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) while (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct irq_bucket *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) next = p->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) generic_handle_irq(p->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) p = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) release_sbi(SBI2DEVID(sbino), slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pt_regs *old_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* SBUS IRQ level (1 - 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int sbusl = pil_to_sbus[pil];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* FIXME: Is this necessary?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cc_get_ipen();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cc_set_iclr(1 << pil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Check IPI data structures after IRQ has been cleared. Hard and Soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * IRQ can happen at the same time, so both cases are always handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (pil == SUN4D_IPI_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sun4d_ipi_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (sbusl == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* cpu interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct irq_bucket *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) p = irq_map[pil];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) while (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct irq_bucket *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) next = p->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) generic_handle_irq(p->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) p = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* SBUS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sun4d_sbus_handler_irq(sbusl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void sun4d_mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct sun4d_handler_data *handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int cpuid = handler_data->cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) real_irq = handler_data->real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_lock_irqsave(&sun4d_imsk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) | (1 << real_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cc_set_imsk(cc_get_imsk() | (1 << real_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void sun4d_unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct sun4d_handler_data *handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int cpuid = handler_data->cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) real_irq = handler_data->real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_lock_irqsave(&sun4d_imsk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cc_set_imsk_other(cpuid, cc_get_imsk_other(cpuid) & ~(1 << real_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cc_set_imsk(cc_get_imsk() & ~(1 << real_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static unsigned int sun4d_startup_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) irq_link(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sun4d_unmask_irq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void sun4d_shutdown_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sun4d_mask_irq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) irq_unlink(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct irq_chip sun4d_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "sun4d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .irq_startup = sun4d_startup_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .irq_shutdown = sun4d_shutdown_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .irq_unmask = sun4d_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .irq_mask = sun4d_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Setup IRQ distribution scheme. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void __init sun4d_distribute_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int cpuid = cpu_logical_map(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (cpuid == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cpuid = cpu_logical_map(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) for_each_node_by_name(dp, "sbi") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int devid = of_getintprop_default(dp, "device-id", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int board = of_getintprop_default(dp, "board#", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) board_to_cpu[board] = cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) set_sbi_tid(devid, cpuid << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) printk(KERN_ERR "All sbus IRQs directed to CPU%d\n", cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void sun4d_clear_clock_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sbus_readl(&sun4d_timers->l10_timer_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void sun4d_load_profile_irq(int cpu, unsigned int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int value = limit ? timer_value(limit) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bw_set_prof_limit(cpu, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void __init sun4d_load_profile_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int cpu = 0, mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) while (!cpu_find_by_instance(cpu, NULL, &mid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sun4d_load_profile_irq(mid >> 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cpu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static unsigned int _sun4d_build_device_irq(unsigned int real_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int pil,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int board)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct sun4d_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) irq = irq_alloc(real_irq, pil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) prom_printf("IRQ: allocate for %d %d %d failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) real_irq, pil, board);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) handler_data = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (unlikely(handler_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) handler_data = kzalloc(sizeof(struct sun4d_handler_data), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (unlikely(!handler_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) prom_printf("IRQ: kzalloc(sun4d_handler_data) failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) handler_data->cpuid = board_to_cpu[board];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) handler_data->real_irq = real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) irq_set_chip_and_handler_name(irq, &sun4d_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) handle_level_irq, "level");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) irq_set_handler_data(irq, handler_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static unsigned int sun4d_build_device_irq(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int real_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device_node *board_parent, *bus = dp->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) char *bus_connection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) const struct linux_prom_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int pil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int board, slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int sbusl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) irq = real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) while (bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (of_node_name_eq(bus, "sbi")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bus_connection = "io-unit";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (of_node_name_eq(bus, "bootbus")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bus_connection = "cpu-unit";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regs = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) slot = regs->which_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * If Bus nodes parent is not io-unit/cpu-unit or the io-unit/cpu-unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * lacks a "board#" property, something is very wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!of_node_name_eq(bus->parent, bus_connection)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) printk(KERN_ERR "%pOF: Error, parent is not %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bus, bus_connection);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) board_parent = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) board = of_getintprop_default(board_parent, "board#", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (board == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) printk(KERN_ERR "%pOF: Error, lacks board# property.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) board_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sbusl = pil_to_sbus[real_irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (sbusl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pil = sun4d_encode_irq(board, sbusl, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pil = real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) irq = _sun4d_build_device_irq(real_irq, pil, board);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static unsigned int sun4d_build_timer_irq(unsigned int board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int real_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return _sun4d_build_device_irq(real_irq, real_irq, board);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void __init sun4d_fixup_trap_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Adjust so that we jump directly to smp4d_ticker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) lvl14_save[2] += smp4d_ticker - real_irq_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* For SMP we use the level 14 ticker, however the bootup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * has copied the firmware's level 14 vector into the boot cpu's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * trap table, we must fix this now or we get squashed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) trap_table->inst_one = lvl14_save[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) trap_table->inst_two = lvl14_save[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) trap_table->inst_three = lvl14_save[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) trap_table->inst_four = lvl14_save[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) local_ops->cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void __init sun4d_init_timers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const u32 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dp = of_find_node_by_name(NULL, "cpu-unit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!dp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) prom_printf("sun4d_init_timers: Unable to find cpu-unit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Which cpu-unit we use is arbitrary, we can view the bootbus timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * registers via any cpu's mapping. The first 'reg' property is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * bootbus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) reg = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) prom_printf("sun4d_init_timers: No reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) board = of_getintprop_default(dp, "board#", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (board == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) prom_printf("sun4d_init_timers: No board# property on cpu-unit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) of_node_put(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) res.start = reg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) res.end = reg[2] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) res.flags = reg[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sun4d_timers = of_ioremap(&res, BW_TIMER_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sizeof(struct sun4d_timer_regs), "user timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!sun4d_timers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) prom_printf("sun4d_init_timers: Can't map timer regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sparc_config.features |= FEAT_L10_CLOCKEVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sparc_config.features |= FEAT_L10_CLOCKSOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sbus_writel(timer_value(sparc_config.cs_period),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &sun4d_timers->l10_timer_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) master_l10_counter = &sun4d_timers->l10_cur_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sun4d_load_profile_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) sun4d_fixup_trap_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) void __init sun4d_init_sbi_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int target_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) target_cpu = boot_cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for_each_node_by_name(dp, "sbi") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int devid = of_getintprop_default(dp, "device-id", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int board = of_getintprop_default(dp, "board#", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) set_sbi_tid(devid, target_cpu << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) board_to_cpu[board] = target_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Get rid of pending irqs from PROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mask = acquire_sbi(devid, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) printk(KERN_ERR "Clearing pending IRQs %08x on SBI %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mask, board);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) release_sbi(devid, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void __init sun4d_init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sparc_config.init_timers = sun4d_init_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sparc_config.build_device_irq = sun4d_build_device_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sparc_config.clock_rate = SBUS_CLOCK_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sparc_config.clear_clock_irq = sun4d_clear_clock_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sparc_config.load_profile_irq = sun4d_load_profile_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Cannot enable interrupts until OBP ticker is disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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