^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/sparc64/kernel/setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/user.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kdev_t.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/inet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/root_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/initrd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/start_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <uapi/linux/mount.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/idprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/starfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/ns87303.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/btext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/mdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_IP_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <net/ipconfig.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "entry.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * operations in asm/ns87303.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_SPINLOCK(ns87303_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) EXPORT_SYMBOL(ns87303_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct screen_info screen_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0, 0, /* orig-x, orig-y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0, /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0, /* orig-video-page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0, /* orig-video-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 128, /* orig-video-cols */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0, 0, 0, /* unused, ega_bx, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 54, /* orig-video-lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0, /* orig-video-isVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 16 /* orig-video-points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) prom_console_write(struct console *con, const char *s, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) prom_write(s, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Exported for mm/init.c:paging_init. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long cmdline_memory_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static struct console prom_early_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "earlyprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .write = prom_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Process kernel command line switches that are specific to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * SPARC or that require special low-level processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void __init process_switch(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) switch (c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 'd':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case 's':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case 'h':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) prom_printf("boot_flags_init: Halt!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case 'p':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) prom_early_console.flags &= ~CON_BOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case 'P':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Force UltraSPARC-III P-Cache on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (tlb_type != cheetah) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) printk("BOOT: Ignoring P-Cache force option.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cheetah_pcache_forced_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cheetah_enable_pcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) printk("Unknown boot switch (-%c)\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void __init boot_flags_init(char *commands)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) while (*commands) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Move to the start of the next "argument". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) while (*commands == ' ')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) commands++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Process any command switches, otherwise skip it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (*commands == '\0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (*commands == '-') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) commands++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) while (*commands && *commands != ' ')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) process_switch(*commands++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!strncmp(commands, "mem=", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cmdline_memory_size = memparse(commands + 4, &commands);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) while (*commands && *commands != ' ')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) commands++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern unsigned short root_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) extern unsigned short root_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) extern unsigned short ram_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RAMDISK_IMAGE_START_MASK 0x07FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RAMDISK_PROMPT_FLAG 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RAMDISK_LOAD_FLAG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) extern int root_mountflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) char reboot_command[COMMAND_LINE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void __init per_cpu_patch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct cpuid_patch_entry *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int is_jbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (tlb_type == spitfire && !this_is_starfire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) is_jbus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (tlb_type != hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __asm__ ("rdpr %%ver, %0" : "=r" (ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (ver >> 32UL) == __SERRANO_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) p = &__cpuid_patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) while (p < &__cpuid_patch_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long addr = p->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int *insns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (tlb_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case spitfire:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) insns = &p->starfire[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case cheetah:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case cheetah_plus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (is_jbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) insns = &p->cheetah_jbus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) insns = &p->cheetah_safari[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case hypervisor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) insns = &p->sun4v[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) prom_printf("Unknown cpu type, halting.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *(unsigned int *) (addr + 0) = insns[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __asm__ __volatile__("flush %0" : : "r" (addr + 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *(unsigned int *) (addr + 4) = insns[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __asm__ __volatile__("flush %0" : : "r" (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *(unsigned int *) (addr + 8) = insns[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __asm__ __volatile__("flush %0" : : "r" (addr + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *(unsigned int *) (addr + 12) = insns[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __asm__ __volatile__("flush %0" : : "r" (addr + 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct sun4v_1insn_patch_entry *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long addr = start->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *(unsigned int *) (addr + 0) = start->insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __asm__ __volatile__("flush %0" : : "r" (addr + 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sun4v_2insn_patch_entry *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long addr = start->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *(unsigned int *) (addr + 0) = start->insns[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __asm__ __volatile__("flush %0" : : "r" (addr + 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *(unsigned int *) (addr + 4) = start->insns[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __asm__ __volatile__("flush %0" : : "r" (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct sun4v_2insn_patch_entry *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long addr = start->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *(unsigned int *) (addr + 0) = start->insns[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __asm__ __volatile__("flush %0" : : "r" (addr + 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *(unsigned int *) (addr + 4) = start->insns[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __asm__ __volatile__("flush %0" : : "r" (addr + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void __init sun4v_patch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) extern void sun4v_hvapi_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (tlb_type != hypervisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sun4v_patch_1insn_range(&__sun4v_1insn_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) &__sun4v_1insn_patch_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) sun4v_patch_2insn_range(&__sun4v_2insn_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &__sun4v_2insn_patch_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (sun4v_chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case SUN4V_CHIP_SPARC_M7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case SUN4V_CHIP_SPARC_M8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case SUN4V_CHIP_SPARC_SN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sun4v_patch_1insn_range(&__sun_m7_1insn_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) &__sun_m7_1insn_patch_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) &__sun_m7_2insn_patch_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) &__fast_win_ctrl_1insn_patch_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) sun4v_hvapi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void __init popc_patch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct popc_3insn_patch_entry *p3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct popc_6insn_patch_entry *p6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) p3 = &__popc_3insn_patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) while (p3 < &__popc_3insn_patch_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned long i, addr = p3->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *(unsigned int *) (addr + (i * 4)) = p3->insns[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __asm__ __volatile__("flush %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) : : "r" (addr + (i * 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) p3++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) p6 = &__popc_6insn_patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) while (p6 < &__popc_6insn_patch_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long i, addr = p6->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *(unsigned int *) (addr + (i * 4)) = p6->insns[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __asm__ __volatile__("flush %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) : : "r" (addr + (i * 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) p6++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void __init pause_patch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct pause_patch_entry *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) p = &__pause_3insn_patch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) while (p < &__pause_3insn_patch_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long i, addr = p->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *(unsigned int *) (addr + (i * 4)) = p->insns[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __asm__ __volatile__("flush %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) : : "r" (addr + (i * 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void __init start_early_boot(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) check_if_starfire();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) per_cpu_patch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) sun4v_patch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) smp_init_cpu_poke();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cpu = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (cpu >= NR_CPUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cpu, NR_CPUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) current_thread_info()->cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) time_init_early();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) prom_init_report();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) start_kernel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* On Ultra, we support all of the v8 capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) HWCAP_SPARC_V9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) EXPORT_SYMBOL(sparc64_elf_hwcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const char *hwcaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "flush", "stbar", "swap", "muldiv", "v9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "ultra3", "blkinit", "n2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* These strings are as they appear in the machine description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * 'hwcap-list' property for cpu nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "adp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const char *crypto_hwcaps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "sha512", "mpmul", "montmul", "montsqr", "crc32c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void cpucap_info(struct seq_file *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned long caps = sparc64_elf_hwcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i, printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) seq_puts(m, "cpucaps\t\t: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long bit = 1UL << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (hwcaps[i] && (caps & bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) seq_printf(m, "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) printed ? "," : "", hwcaps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) printed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (caps & HWCAP_SPARC_CRYPTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long cfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned long bit = 1UL << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (cfr & bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) seq_printf(m, "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) printed ? "," : "", crypto_hwcaps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) printed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void __init report_one_hwcap(int *printed, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if ((*printed) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) printk(KERN_INFO "CPU CAPS: [");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) printk(KERN_CONT "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (*printed) ? "," : "", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (++(*printed) == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) printk(KERN_CONT "]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void __init report_crypto_hwcaps(int *printed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long cfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned long bit = 1UL << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (cfr & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) report_one_hwcap(printed, crypto_hwcaps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void __init report_hwcaps(unsigned long caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int i, printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned long bit = 1UL << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (hwcaps[i] && (caps & bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) report_one_hwcap(&printed, hwcaps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (caps & HWCAP_SPARC_CRYPTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) report_crypto_hwcaps(&printed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (printed != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) printk(KERN_CONT "]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static unsigned long __init mdesc_cpu_hwcap_list(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct mdesc_handle *hp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned long caps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) const char *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u64 pn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hp = mdesc_grab();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (pn == MDESC_NODE_NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int i, plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long bit = 1UL << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) caps |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!strcmp(prop, crypto_hwcaps[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) caps |= HWCAP_SPARC_CRYPTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) plen = strlen(prop) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) prop += plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) len -= plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mdesc_release(hp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* This yields a mask that user programs can use to figure out what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * instruction set this cpu supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void __init init_sparc64_elf_hwcap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long cap = sparc64_elf_hwcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned long mdesc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (tlb_type == cheetah || tlb_type == cheetah_plus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cap |= HWCAP_SPARC_ULTRA3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) else if (tlb_type == hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cap |= HWCAP_SPARC_BLKINIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cap |= HWCAP_SPARC_N2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mdesc_caps = mdesc_cpu_hwcap_list();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!mdesc_caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (tlb_type == spitfire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cap |= AV_SPARC_VIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (tlb_type == cheetah || tlb_type == cheetah_plus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (tlb_type == cheetah_plus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long impl, ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) impl = ((ver >> 32) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (impl == PANTHER_IMPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cap |= AV_SPARC_POPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (tlb_type == hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) cap |= AV_SPARC_ASI_BLK_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) AV_SPARC_ASI_BLK_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) AV_SPARC_POPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) sun4v_chip_type == SUN4V_CHIP_SPARC64X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) AV_SPARC_FMAF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) sparc64_elf_hwcap = cap | mdesc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) report_hwcaps(sparc64_elf_hwcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (sparc64_elf_hwcap & AV_SPARC_POPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) popc_patch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pause_patch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) void __init alloc_irqstack_bootmem(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned int i, node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for_each_possible_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) node = cpu_to_node(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) softirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) THREAD_SIZE, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!softirq_stack[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) __func__, THREAD_SIZE, THREAD_SIZE, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) hardirq_stack[i] = memblock_alloc_node(THREAD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) THREAD_SIZE, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!hardirq_stack[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) panic("%s: Failed to allocate %lu bytes align=%lx nid=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) __func__, THREAD_SIZE, THREAD_SIZE, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Initialize PROM console and command line. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *cmdline_p = prom_getbootargs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) parse_early_param();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) boot_flags_init(*cmdline_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #ifdef CONFIG_EARLYFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (btext_find_display())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) register_console(&prom_early_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (tlb_type == hypervisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) pr_info("ARCH: SUN4V\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pr_info("ARCH: SUN4U\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) idprom_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!root_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) root_mountflags &= ~MS_RDONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ROOT_DEV = old_decode_dev(root_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #ifdef CONFIG_BLK_DEV_RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) task_thread_info(&init_task)->kregs = &fake_swapper_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #ifdef CONFIG_IP_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!ic_set_manually) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) phandle chosen = prom_finddevice("/chosen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u32 cl, sv, gw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) cl = prom_getintdefault (chosen, "client-ip", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) sv = prom_getintdefault (chosen, "server-ip", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) gw = prom_getintdefault (chosen, "gateway-ip", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (cl && sv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ic_myaddr = cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ic_servaddr = sv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (gw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ic_gateway = gw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ic_proto_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Get boot processor trap_block[] setup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) init_cur_cpu_trap(current_thread_info());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) paging_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) init_sparc64_elf_hwcap();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) smp_fill_in_cpu_possible_map();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Once the OF device tree and MDESC have been setup and nr_cpus has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * been parsed, we know the list of possible cpus. Therefore we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * allocate the IRQ stacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) alloc_irqstack_bootmem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) extern int stop_a_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) void sun_do_break(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!stop_a_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) prom_printf("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) flush_user_windows();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) prom_cmdline();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) EXPORT_SYMBOL(sun_do_break);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int stop_a_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) EXPORT_SYMBOL(stop_a_enabled);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags