^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sbus.c: UltraSparc SBUS controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/numa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/upa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/starfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "iommu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAP_BASE ((u32)0xc0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Offsets from iommu_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SYSIO_IOMMUREG_BASE 0x2400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IOMMU_DRAM_VALID (1UL << 30UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Offsets from strbuf_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SYSIO_STRBUFREG_BASE 0x2800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STRBUF_TAG_VALID 0x02UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Enable 64-bit DVMA mode for the given device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void sbus_set_sbus64(struct device *dev, int bursts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct iommu *iommu = dev->archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct platform_device *op = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct linux_prom_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regs = of_get_property(op->dev.of_node, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) slot = regs->which_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) cfg_reg = iommu->write_complete_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) switch (slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cfg_reg += 0x20UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) cfg_reg += 0x28UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cfg_reg += 0x30UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cfg_reg += 0x38UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cfg_reg += 0x40UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) cfg_reg += 0x48UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cfg_reg += 0x50UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val = upa_readq(cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (val & (1UL << 14UL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Extended transfer mode already enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val |= (1UL << 14UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (bursts & DMA_BURST8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val |= (1UL << 1UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (bursts & DMA_BURST16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val |= (1UL << 2UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (bursts & DMA_BURST32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val |= (1UL << 3UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (bursts & DMA_BURST64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val |= (1UL << 4UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) upa_writeq(val, cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXPORT_SYMBOL(sbus_set_sbus64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* INO number to IMAP register offset for SYSIO external IRQ's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * This should conform to both Sunfire/Wildfire server and Fusion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * desktop designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SYSIO_IMAP_SLOT0 0x2c00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SYSIO_IMAP_SLOT1 0x2c08UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SYSIO_IMAP_SLOT2 0x2c10UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SYSIO_IMAP_SLOT3 0x2c18UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SYSIO_IMAP_SCSI 0x3000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SYSIO_IMAP_ETH 0x3008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SYSIO_IMAP_BPP 0x3010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SYSIO_IMAP_AUDIO 0x3018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SYSIO_IMAP_PFAIL 0x3020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SYSIO_IMAP_KMS 0x3028UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SYSIO_IMAP_FLPY 0x3030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SYSIO_IMAP_SHW 0x3038UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SYSIO_IMAP_KBD 0x3040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SYSIO_IMAP_MS 0x3048UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SYSIO_IMAP_SER 0x3050UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SYSIO_IMAP_TIM0 0x3060UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SYSIO_IMAP_TIM1 0x3068UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SYSIO_IMAP_UE 0x3070UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SYSIO_IMAP_CE 0x3078UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SYSIO_IMAP_SBERR 0x3080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SYSIO_IMAP_PMGMT 0x3088UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SYSIO_IMAP_GFX 0x3090UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SYSIO_IMAP_EUPA 0x3098UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define bogon ((unsigned long) -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static unsigned long sysio_irq_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* SBUS Slot 0 --> 3, level 1 --> 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Onboard devices (not relevant/used on SunFire). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SYSIO_IMAP_SCSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SYSIO_IMAP_ETH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SYSIO_IMAP_BPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SYSIO_IMAP_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SYSIO_IMAP_PFAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SYSIO_IMAP_KMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SYSIO_IMAP_FLPY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SYSIO_IMAP_SHW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SYSIO_IMAP_KBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SYSIO_IMAP_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SYSIO_IMAP_SER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SYSIO_IMAP_TIM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SYSIO_IMAP_TIM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bogon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SYSIO_IMAP_UE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SYSIO_IMAP_CE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SYSIO_IMAP_SBERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SYSIO_IMAP_PMGMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #undef bogon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Convert Interrupt Mapping register pointer to associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Interrupt Clear register pointer, SYSIO specific version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SYSIO_ICLR_UNUSED0 0x3400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SYSIO_ICLR_SLOT0 0x3408UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SYSIO_ICLR_SLOT1 0x3448UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SYSIO_ICLR_SLOT2 0x3488UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SYSIO_ICLR_SLOT3 0x34c8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static unsigned long sysio_imap_to_iclr(unsigned long imap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return imap + diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct iommu *iommu = op->dev.archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long imap, iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int sbus_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) imap = sysio_irq_offsets[ino];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (imap == ((unsigned long)-1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) imap += reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* SYSIO inconsistency. For external SLOTS, we have to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * the right ICLR register based upon the lower SBUS irq level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ino >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) iclr = sysio_imap_to_iclr(imap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int sbus_slot = (ino & 0x18)>>3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sbus_level = ino & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) switch(sbus_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) iclr = reg_base + SYSIO_ICLR_SLOT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) iclr = reg_base + SYSIO_ICLR_SLOT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) iclr = reg_base + SYSIO_ICLR_SLOT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) iclr = reg_base + SYSIO_ICLR_SLOT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return build_irq(sbus_level, iclr, imap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Error interrupt handling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SYSIO_UE_AFSR 0x0030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SYSIO_UE_AFAR 0x0038UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct platform_device *op = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct iommu *iommu = op->dev.archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long afsr_reg, afar_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int reported, portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) afsr_reg = reg_base + SYSIO_UE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) afar_reg = reg_base + SYSIO_UE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Latch error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) portid = of_getintprop_default(op->dev.of_node, "portid", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (((error_bits & SYSIO_UEAFSR_PPIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "PIO" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ((error_bits & SYSIO_UEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "DVMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ((error_bits & SYSIO_UEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "DVMA Write" : "???")))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (afsr & SYSIO_UEAFSR_MID) >> 37UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) printk("SYSIO[%x]: Secondary UE errors [", portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (afsr & SYSIO_UEAFSR_SPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) printk("(PIO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (afsr & SYSIO_UEAFSR_SDRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) printk("(DVMA Read)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (afsr & SYSIO_UEAFSR_SDWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) printk("(DVMA Write)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SYSIO_CE_AFSR 0x0040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SYSIO_CE_AFAR 0x0048UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct platform_device *op = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct iommu *iommu = op->dev.archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long afsr_reg, afar_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int reported, portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) afsr_reg = reg_base + SYSIO_CE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) afar_reg = reg_base + SYSIO_CE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Latch error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) portid = of_getintprop_default(op->dev.of_node, "portid", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (((error_bits & SYSIO_CEAFSR_PPIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "PIO" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ((error_bits & SYSIO_CEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "DVMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ((error_bits & SYSIO_CEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "DVMA Write" : "???")))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* XXX Use syndrome and afar to print out module string just like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * XXX UDB CE trap handler does... -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (afsr & SYSIO_CEAFSR_MID) >> 37UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) printk("SYSIO[%x]: Secondary CE errors [", portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (afsr & SYSIO_CEAFSR_SPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) printk("(PIO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (afsr & SYSIO_CEAFSR_SDRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) printk("(DVMA Read)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (afsr & SYSIO_CEAFSR_SDWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) printk("(DVMA Write)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SYSIO_SBUS_AFSR 0x2010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SYSIO_SBUS_AFAR 0x2018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct platform_device *op = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct iommu *iommu = op->dev.archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long afsr_reg, afar_reg, reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int reported, portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) reg_base = iommu->write_complete_reg - 0x2000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) afsr_reg = reg_base + SYSIO_SBUS_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) afar_reg = reg_base + SYSIO_SBUS_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) portid = of_getintprop_default(op->dev.of_node, "portid", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) (((error_bits & SYSIO_SBAFSR_PLE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "Late PIO Error" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ((error_bits & SYSIO_SBAFSR_PTO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "Time Out" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ((error_bits & SYSIO_SBAFSR_PBERR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "Error Ack" : "???")))),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (afsr & SYSIO_SBAFSR_MID) >> 37UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) printk("SYSIO[%x]: Secondary SBUS errors [", portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (afsr & SYSIO_SBAFSR_SLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) printk("(Late PIO Error)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (afsr & SYSIO_SBAFSR_STO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) printk("(Time Out)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (afsr & SYSIO_SBAFSR_SBERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) printk("(Error Ack)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* XXX check iommu/strbuf for further error status XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ECC_CONTROL 0x0020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SYSIO_UE_INO 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SYSIO_CE_INO 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SYSIO_SBUSERR_INO 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void __init sysio_register_error_handlers(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct iommu *iommu = op->dev.archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) portid = of_getintprop_default(op->dev.of_node, "portid", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) irq = sbus_build_irq(op, SYSIO_UE_INO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (request_irq(irq, sysio_ue_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "SYSIO_UE", op) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) irq = sbus_build_irq(op, SYSIO_CE_INO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (request_irq(irq, sysio_ce_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "SYSIO_CE", op) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (request_irq(irq, sysio_sbus_error_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "SYSIO_SBERR", op) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Now turn the error interrupts on and also enable ECC checking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) upa_writeq((SYSIO_ECNTRL_ECCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SYSIO_ECNTRL_UEEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) SYSIO_ECNTRL_CEEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) reg_base + ECC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) control = upa_readq(iommu->write_complete_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) control |= 0x100UL; /* SBUS Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) upa_writeq(control, iommu->write_complete_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Boot time initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void __init sbus_iommu_init(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) const struct linux_prom64_registers *pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct strbuf *strbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned long regs, reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int i, portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pr = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!pr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) prom_printf("sbus_iommu_init: Cannot map SYSIO "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "control registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) regs = pr->phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!iommu || !strbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto fatal_memory_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) op->dev.archdata.iommu = iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) op->dev.archdata.stc = strbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) op->dev.archdata.numa_node = NUMA_NO_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) reg_base = regs + SYSIO_IOMMUREG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) iommu->iommu_control = reg_base + IOMMU_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) iommu->iommu_flush = reg_base + IOMMU_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) iommu->iommu_tags = iommu->iommu_control +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) (IOMMU_TAGDIAG - IOMMU_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) reg_base = regs + SYSIO_STRBUFREG_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) strbuf->strbuf_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) strbuf->strbuf_flushflag = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ((((unsigned long)&strbuf->__flushflag_buf[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) + 63UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) & ~63UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) strbuf->strbuf_flushflag_pa = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __pa(strbuf->strbuf_flushflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* The SYSIO SBUS control register is used for dummy reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * in order to ensure write completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) iommu->write_complete_reg = regs + 0x2000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) portid = of_getintprop_default(op->dev.of_node, "portid", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) portid, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto fatal_memory_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) control = upa_readq(iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) control = ((7UL << 16UL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) (0UL << 2UL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) (1UL << 1UL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) (1UL << 0UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) upa_writeq(control, iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Clean out any cruft in the IOMMU using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * diagnostic accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned long dram, tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dram += (unsigned long)i * 8UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tag += (unsigned long)i * 8UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) upa_writeq(0, dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) upa_writeq(0, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) upa_readq(iommu->write_complete_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Give the TSB to SYSIO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Setup streaming buffer, DE=1 SB_EN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) control = (1UL << 1UL) | (1UL << 0UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) upa_writeq(control, strbuf->strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Clear out the tags using diagnostics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned long ptag, ltag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ptag = strbuf->strbuf_control +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (STRBUF_PTAGDIAG - STRBUF_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ltag = strbuf->strbuf_control +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (STRBUF_LTAGDIAG - STRBUF_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ptag += (unsigned long)i * 8UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ltag += (unsigned long)i * 8UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) upa_writeq(0UL, ptag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) upa_writeq(0UL, ltag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Enable DVMA arbitration for all devices/slots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) control = upa_readq(iommu->write_complete_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) control |= 0x3fUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) upa_writeq(control, iommu->write_complete_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Now some Xfire specific grot... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (this_is_starfire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) starfire_hookup(portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) sysio_register_error_handlers(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fatal_memory_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) kfree(iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) kfree(strbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int __init sbus_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for_each_node_by_name(dp, "sbus") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct platform_device *op = of_find_device_by_node(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) sbus_iommu_init(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) of_propagate_archdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) subsys_initcall(sbus_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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