^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pcr.c: Generic sparc64 performance counter infrastructure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq_work.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ftrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/pil.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pcr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/nmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* This code is shared between various users of the performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * counters. Users will be oprofile, pseudo-NMI watchdog, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * perf_event support layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Performance counter interrupts run unmasked at PIL level 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Therefore we can't do things like wakeups and other work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * that expects IRQ disabling to be adhered to in locking etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Therefore in such situations we defer the work by signalling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * a lower level cpu IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pt_regs *old_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) clear_softint(1 << PIL_DEFERRED_PCR_WORK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifdef CONFIG_IRQ_WORK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) irq_work_run();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void arch_irq_work_raise(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) set_softint(1 << PIL_DEFERRED_PCR_WORK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const struct pcr_ops *pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EXPORT_SYMBOL_GPL(pcr_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u64 direct_pcr_read(unsigned long reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) WARN_ON_ONCE(reg_num != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __asm__ __volatile__("rd %%pcr, %0" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void direct_pcr_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) WARN_ON_ONCE(reg_num != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static u64 direct_pic_read(unsigned long reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) WARN_ON_ONCE(reg_num != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __asm__ __volatile__("rd %%pic, %0" : "=r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void direct_pic_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) WARN_ON_ONCE(reg_num != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Blackbird errata workaround. See commentary in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __asm__ __volatile__("ba,pt %%xcc, 99f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) " nop\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ".align 64\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "99:wr %0, 0x0, %%pic\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "rd %%pic, %%g0" : : "r" (val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static u64 direct_picl_value(unsigned int nmi_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 delta = local_cpu_data().clock_tick / nmi_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ((u64)((0 - delta) & 0xffffffff)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct pcr_ops direct_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .read_pcr = direct_pcr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .write_pcr = direct_pcr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .read_pic = direct_pic_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .write_pic = direct_pic_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .nmi_picl_value = direct_picl_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pcr_nmi_enable = (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pcr_nmi_disable = PCR_PIC_PRIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void n2_pcr_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) WARN_ON_ONCE(reg_num != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (val & PCR_N2_HTRACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) direct_pcr_write(reg_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) direct_pcr_write(reg_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static u64 n2_picl_value(unsigned int nmi_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 delta = local_cpu_data().clock_tick / (nmi_hz << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ((u64)((0 - delta) & 0xffffffff)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct pcr_ops n2_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .read_pcr = direct_pcr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .write_pcr = n2_pcr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .read_pic = direct_pic_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .write_pic = direct_pic_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .nmi_picl_value = n2_picl_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .pcr_nmi_enable = (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PCR_N2_TOE_OV1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (2 << PCR_N2_SL1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (0xff << PCR_N2_MASK1_SHIFT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .pcr_nmi_disable = PCR_PIC_PRIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static u64 n4_pcr_read(unsigned long reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (void) sun4v_vt_get_perfreg(reg_num, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void n4_pcr_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (void) sun4v_vt_set_perfreg(reg_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static u64 n4_pic_read(unsigned long reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) : "=r" (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) : "r" (reg_num * 0x8UL), "i" (ASI_PIC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void n4_pic_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __asm__ __volatile__("stxa %0, [%1] %2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) : "r" (val), "r" (reg_num * 0x8UL), "i" (ASI_PIC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static u64 n4_picl_value(unsigned int nmi_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 delta = local_cpu_data().clock_tick / (nmi_hz << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ((u64)((0 - delta) & 0xffffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct pcr_ops n4_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .read_pcr = n4_pcr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .write_pcr = n4_pcr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .read_pic = n4_pic_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .write_pic = n4_pic_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .nmi_picl_value = n4_picl_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PCR_N4_UTRACE | PCR_N4_TOE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (26 << PCR_N4_SL_SHIFT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .pcr_nmi_disable = PCR_N4_PICNPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static u64 n5_pcr_read(unsigned long reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (void) sun4v_t5_get_perfreg(reg_num, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void n5_pcr_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (void) sun4v_t5_set_perfreg(reg_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct pcr_ops n5_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .read_pcr = n5_pcr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .write_pcr = n5_pcr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .read_pic = n4_pic_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .write_pic = n4_pic_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .nmi_picl_value = n4_picl_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PCR_N4_UTRACE | PCR_N4_TOE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (26 << PCR_N4_SL_SHIFT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .pcr_nmi_disable = PCR_N4_PICNPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static u64 m7_pcr_read(unsigned long reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) (void) sun4v_m7_get_perfreg(reg_num, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void m7_pcr_write(unsigned long reg_num, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (void) sun4v_m7_set_perfreg(reg_num, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct pcr_ops m7_pcr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .read_pcr = m7_pcr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .write_pcr = m7_pcr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .read_pic = n4_pic_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .write_pic = n4_pic_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .nmi_picl_value = n4_picl_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PCR_N4_UTRACE | PCR_N4_TOE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (26 << PCR_N4_SL_SHIFT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .pcr_nmi_disable = PCR_N4_PICNPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static unsigned long perf_hsvc_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static unsigned long perf_hsvc_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static unsigned long perf_hsvc_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int __init register_perf_hsvc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long hverror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (tlb_type == hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (sun4v_chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case SUN4V_CHIP_NIAGARA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) perf_hsvc_group = HV_GRP_NIAG_PERF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case SUN4V_CHIP_NIAGARA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) perf_hsvc_group = HV_GRP_N2_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case SUN4V_CHIP_NIAGARA3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) perf_hsvc_group = HV_GRP_KT_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case SUN4V_CHIP_NIAGARA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) perf_hsvc_group = HV_GRP_VT_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case SUN4V_CHIP_NIAGARA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) perf_hsvc_group = HV_GRP_T5_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case SUN4V_CHIP_SPARC_M7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) perf_hsvc_group = HV_GRP_M7_PERF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) perf_hsvc_major = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) perf_hsvc_minor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) hverror = sun4v_hvapi_register(perf_hsvc_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) perf_hsvc_major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) &perf_hsvc_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (hverror) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_err("perfmon: Could not register hvapi(0x%lx).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) hverror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void __init unregister_perf_hsvc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (tlb_type != hypervisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sun4v_hvapi_unregister(perf_hsvc_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int __init setup_sun4v_pcr_ops(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch (sun4v_chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case SUN4V_CHIP_NIAGARA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case SUN4V_CHIP_NIAGARA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case SUN4V_CHIP_NIAGARA3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pcr_ops = &n2_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case SUN4V_CHIP_NIAGARA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pcr_ops = &n4_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case SUN4V_CHIP_NIAGARA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pcr_ops = &n5_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case SUN4V_CHIP_SPARC_M7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pcr_ops = &m7_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int __init pcr_arch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int err = register_perf_hsvc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (tlb_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case hypervisor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err = setup_sun4v_pcr_ops();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case cheetah:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case cheetah_plus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pcr_ops = &direct_pcr_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case spitfire:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* UltraSPARC-I/II and derivatives lack a profile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * counter overflow interrupt so we can't make use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * their hardware currently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto out_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return nmi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) out_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unregister_perf_hsvc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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