^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pcic.c: MicroSPARC-IIep PCI controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 V. Roganov and G. Raiko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Code is derived from Ultra/PCI PSYCHO controller support, see that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for author info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Support for diverse IIep based platforms by Pete Zaitcev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * CP-1200 by Eric Brower.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/swift.h> /* for cache flushing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/pcic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/irq_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * I studied different documents and many live PROMs both from 2.30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * family and 3.xx versions. I came to the amazing conclusion: there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * absolutely no way to route interrupts in IIep systems relying on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * information which PROM presents. We must hardcode interrupt routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * schematics. And this actually sucks. -- zaitcev 1999/05/12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * To find irq for a device we determine which routing map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * is in effect or, in other words, on which machine we are running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * We use PROM name for this although other techniques may be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * in special cases (Gleb reports a PROMless IIep based system).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Once we know the map we take device configuration address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * find PCIC pin number where INT line goes. Then we may either program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * preferred irq into the PCIC or supply the preexisting irq to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pcic_ca2irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned char busno; /* PCI bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned char devfn; /* Configuration address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char pin; /* PCIC external interrupt pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int force; /* Enforce preferred IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pcic_sn2list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) char *sysname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct pcic_ca2irq *intmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int mapdim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * JavaEngine-1 apparently has different versions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * According to communications with Sun folks, for P2 build 501-4628-03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * pin 0 - parallel, audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * pin 1 - Ethernet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * pin 2 - su;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * pin 3 - PS/2 kbd and mouse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * OEM manual (805-1486):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * pin 0: Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * pin 1: All EBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * pin 2: IGA (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * pin 3: Not connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * OEM manual says that 501-4628 & 501-4811 are the same thing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * only the latter has NAND flash in place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * So far unofficial Sun wins over the OEM manual. Poor OEMs...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct pcic_ca2irq pcic_i_jse[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 0, 0x01, 1, 6, 0 }, /* hme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0, 0x80, 5, 11, 0 }, /* EIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0, 0xA0, 4, 9, 0 }, /* USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Some pins belong to non-PCI devices, we hardcode them in drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * sun4m timers - irq 10, 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * PC style RTC - pin 7, irq 4 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Smart card, Parallel - pin 4 shared with USB, ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * audio - pin 3, irq 5 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* SPARCengine-6 was the original release name of CP1200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The documentation differs between the two versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct pcic_ca2irq pcic_i_se6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0, 0x08, 0, 2, 0 }, /* SCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0, 0x01, 1, 6, 0 }, /* HME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0, 0x00, 3, 13, 0 }, /* EBus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Krups (courtesy of Varol Kaptan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * No documentation available, but it was easy to guess
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * because it was very similar to Espresso.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * pin 0 - kbd, mouse, serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * pin 1 - Ethernet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * pin 2 - igs (we do not use it);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * pin 3 - audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * pin 4,5,6 - unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * pin 7 - RTC (from P2 onwards as David B. says).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct pcic_ca2irq pcic_i_jk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0, 0x01, 1, 6, 0 }, /* hme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Several entries in this list may point to the same routing map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * as several PROMs may be installed on the same physical board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SN2L_INIT(name, map) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { name, map, ARRAY_SIZE(map) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct pcic_sn2list pcic_known_sysnames[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { NULL, NULL, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Only one PCIC per IIep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * and since we have no SMP IIep, only one per system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int pcic0_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct linux_pcic pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void __iomem *pcic_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static volatile int pcic_speculative;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static volatile int pcic_trapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int pcic_build_device_irq(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int real_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int where, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct linux_pcic *pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pcic = &pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #if 0 /* does not fail here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pcic_speculative = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pcic_trapped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #if 0 /* does not fail here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (pcic_trapped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *value = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pcic_speculative = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pcic_trapped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *value = readl(pcic->pcic_config_space_data + (where&4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (pcic_trapped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pcic_speculative = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *value = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pcic_speculative = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (bus->number != 0) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pcic_read_config_dword(bus->number, devfn, where&~3, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *val = 0xff & (v >> (8*(where & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (where&1) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pcic_read_config_dword(bus->number, devfn, where&~3, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *val = 0xffff & (v >> (8*(where & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (where&3) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pcic_read_config_dword(bus->number, devfn, where&~3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int where, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct linux_pcic *pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pcic = &pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(value, pcic->pcic_config_space_data + (where&4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (bus->number != 0) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pcic_read_config_dword(bus->number, devfn, where&~3, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) v = (v & ~(0xff << (8*(where&3)))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ((0xff&val) << (8*(where&3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return pcic_write_config_dword(bus->number, devfn, where&~3, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (where&1) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pcic_read_config_dword(bus->number, devfn, where&~3, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) v = (v & ~(0xffff << (8*(where&3)))) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ((0xffff&val) << (8*(where&3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return pcic_write_config_dword(bus->number, devfn, where&~3, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (where&3) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return pcic_write_config_dword(bus->number, devfn, where, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct pci_ops pcic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .read = pcic_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .write = pcic_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * On sparc64 pcibios_init() calls pci_controller_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * We want PCIC probed little ahead so that interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * would be operational.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int __init pcic_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct linux_pcic *pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct linux_prom_registers regs[PROMREG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct linux_pbm_info* pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) char namebuf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) phandle node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pcic0_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) prom_printf("PCIC: called twice!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pcic = &pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) node = prom_getchild (prom_root_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) node = prom_searchsiblings (node, "pci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (node == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Map in PCIC register set, config space, and IO base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (err == 0 || err == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) prom_printf("PCIC: Error, cannot get PCIC registers "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "from PROM.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pcic0_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pcic->pcic_res_regs.name = "pcic_registers";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!pcic->pcic_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) prom_printf("PCIC: Error, cannot map PCIC registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pcic->pcic_res_io.name = "pcic_io";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if ((pcic->pcic_io = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ioremap(regs[1].phys_addr, 0x10000)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if ((pcic->pcic_config_space_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) prom_printf("PCIC: Error, cannot map "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "PCI Configuration Space Address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Docs say three least significant bits in address and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * must be the same. Thus, we need adjust size of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if ((pcic->pcic_config_space_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) prom_printf("PCIC: Error, cannot map "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "PCI Configuration Space Data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pbm = &pcic->pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pbm->prom_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) strcpy(pbm->prom_name, namebuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) extern int pcic_nmi_trap_patch[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) t_nmi[0] = pcic_nmi_trap_patch[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) t_nmi[1] = pcic_nmi_trap_patch[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) t_nmi[2] = pcic_nmi_trap_patch[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) t_nmi[3] = pcic_nmi_trap_patch[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) swift_flush_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pcic_regs = pcic->pcic_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct pcic_sn2list *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (strcmp(namebuf, p->sysname) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pcic->pcic_imap = p->intmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pcic->pcic_imdim = p->mapdim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (pcic->pcic_imap == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * We do not panic here for the sake of embedded systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) printk("PCIC: System %s is unknown, cannot route interrupts\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) namebuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct linux_pbm_info *pbm = &pcic->pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!pbm->pci_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #if 0 /* deadwood transplanted from sparc64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pci_record_assignments(pbm, pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pci_assign_unassigned(pbm, pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_fixup_irq(pbm, pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_bus_add_devices(pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Main entry point from the PCI subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int __init pcic_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct linux_pcic *pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * PCIC should be initialized at start of the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * So, here we report the presence of PCIC and do some magic passes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if(!pcic0_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pcic = &pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Switch off IOTLB translation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pcic->pcic_regs+PCI_DVMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Increase mapped size for PCI memory space (DMA access).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Should be done in that order (size first, address second).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Why we couldn't set up 4GB and forget about it? XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pcic->pcic_regs+PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pcic_pbm_scan_bus(pcic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int pcic_present(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return pcic0_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct linux_prom_pci_registers regs[PROMREG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) phandle node = prom_getchild(pbm->prom_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) while(node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) err = prom_getproperty(node, "reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) (char *)®s[0], sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if(err != 0 && err != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if(devfn == pdev->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) node = prom_getsibling(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline struct pcidev_cookie *pci_devcookie_alloc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void pcic_map_pci_device(struct linux_pcic *pcic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct pci_dev *dev, int node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) char namebuf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (node == 0 || node == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) strcpy(namebuf, "???");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) for (j = 0; j < 6; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) address = dev->resource[j].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (address == 0) break; /* are sequential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) flags = dev->resource[j].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if ((flags & IORESOURCE_IO) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (address < 0x10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * A device responds to I/O cycles on PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * We generate these cycles with memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * access into the fixed map (phys 0x30000000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Since a device driver does not want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * do ioremap() before accessing PC-style I/O,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * we supply virtual, ready to access address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Note that request_region()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * works for these devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * XXX Neat trick, but it's a *bad* idea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * to shit into regions like that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * What if we want to allocate one more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * PCI base address...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev->resource[j].start =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pcic->pcic_io + address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev->resource[j].end = 1; /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev->resource[j].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * OOPS... PCI Spec allows this. Sun does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * not have any devices getting above 64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * so it must be user with a weird I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * board in a PCI slot. We must remap it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * under 64K but it is not done yet. XXX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pci_info(dev, "PCIC: Skipping I/O space at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "0x%lx, this will Oops if a driver "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "attaches device '%s'\n", address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) namebuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct pcic_ca2irq *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int i, ivec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) char namebuf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (node == 0 || node == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) strcpy(namebuf, "???");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) prom_getstring(node, "name", namebuf, sizeof(namebuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if ((p = pcic->pcic_imap) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) for (i = 0; i < pcic->pcic_imdim; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (p->busno == dev->bus->number && p->devfn == dev->devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (i >= pcic->pcic_imdim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pci_info(dev, "PCIC: device %s not found in %d\n", namebuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pcic->pcic_imdim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) i = p->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (i >= 0 && i < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) real_irq = ivec >> (i << 2) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) } else if (i >= 4 && i < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) real_irq = ivec >> ((i-4) << 2) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else { /* Corrupted map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pci_info(dev, "PCIC: BAD PIN %d\n", i); for (;;) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* real_irq means PROM did not bother to program the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (real_irq == 0 || p->force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pci_info(dev, "PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pci_info(dev, "PCIC: setting irq %d at pin %d\n", p->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) p->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) real_irq = p->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) i = p->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (i >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ivec &= ~(0xF << ((i - 4) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ivec |= p->irq << ((i - 4) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ivec &= ~(0xF << (i << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ivec |= p->irq << (i << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev->irq = pcic_build_device_irq(NULL, real_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Normally called from {do_}pci_scan_bus...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void pcibios_fixup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct linux_pcic *pcic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* struct linux_pbm_info* pbm = &pcic->pbm; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct pcidev_cookie *pcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!pcic0_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) pci_info(bus, "pcibios_fixup_bus: no PCIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pcic = &pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (bus->number != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pci_info(bus, "pcibios_fixup_bus: nonzero bus 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) node = pdev_to_pnode(&pcic->pbm, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if(node == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) node = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* cookies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pcp = pci_devcookie_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pcp->pbm = &pcic->pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pcp->prom_node = of_find_node_by_phandle(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev->sysdata = pcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* fixing I/O to look like memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pcic_map_pci_device(pcic, dev, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pcic_fill_irq(pcic, dev, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int pcibios_enable_device(struct pci_dev *dev, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u16 cmd, oldcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) oldcmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct resource *res = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Only set up the requested stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!(mask & (1<<i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) cmd |= PCI_COMMAND_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (res->flags & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) cmd |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (cmd != oldcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Makes compiler happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static volatile int pcic_timer_dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void pcic_clear_clock_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define USECS_PER_JIFFY (1000000 / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static unsigned int pcic_cycles_offset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 value, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) count = value & ~PCI_SYS_COUNTER_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (value & PCI_SYS_COUNTER_OVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) count += TICK_TIMER_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * We divide all by HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * to have microsecond resolution and to avoid overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Coordinate with the sparc_config.clock_rate setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return count * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) void __init pci_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct linux_pcic *pcic = &pcic0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned long v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int timer_irq, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * The clock_rate is in SBUS dimension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * We take into account this in pcic_cycles_offset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) sparc_config.features |= FEAT_L10_CLOCKEVENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sparc_config.features |= FEAT_L10_CLOCKSOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) sparc_config.get_cycles_offset = pcic_cycles_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* PROM should set appropriate irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) timer_irq = PCI_COUNTER_IRQ_SYS(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) pcic->pcic_regs+PCI_COUNTER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) irq = pcic_build_device_irq(NULL, timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = request_irq(irq, timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) IRQF_TIMER, "timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void watchdog_reset() {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) void pcic_nmi(unsigned int pend, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pend = swab32(pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * XXX On CP-1200 PCI #SERR may happen, we do not know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * what to do about it yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pend, (int)regs->pc, pcic_speculative);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (;;) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pcic_speculative = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pcic_trapped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) regs->pc = regs->npc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) regs->npc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static inline unsigned long get_irqmask(int irq_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 1 << irq_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void pcic_mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned long mask, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mask = (unsigned long)data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void pcic_unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned long mask, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mask = (unsigned long)data->chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static unsigned int pcic_startup_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) irq_link(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pcic_unmask_irq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static struct irq_chip pcic_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .name = "pcic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .irq_startup = pcic_startup_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .irq_mask = pcic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .irq_unmask = pcic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned int pcic_build_device_irq(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unsigned int real_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mask = get_irqmask(real_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) irq = irq_alloc(real_irq, real_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (irq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) irq_set_chip_and_handler_name(irq, &pcic_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) handle_level_irq, "PCIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) irq_set_chip_data(irq, (void *)mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static void pcic_load_profile_irq(int cpu, unsigned int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) void __init sun4m_pci_init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sparc_config.build_device_irq = pcic_build_device_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) sparc_config.clear_clock_irq = pcic_clear_clock_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) sparc_config.load_profile_irq = pcic_load_profile_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) subsys_initcall(pcic_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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