^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/numa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pstate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/upa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "iommu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRIVER_NAME "schizo"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PFX DRIVER_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* This is a convention that at least Excalibur and Merlin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * follow. I suppose the SCHIZO used in Starcat and friends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * will do similar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The only way I could see this changing is if the newlink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * block requires more space in Schizo's address space than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * they predicted, thus requiring an address space reorg when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * the newer Schizo is taped out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Streaming buffer control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* IOMMU control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Schizo config space address format is nearly identical to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * that of PSYCHO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 32 24 23 16 15 11 10 8 7 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * ---------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ---------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (((unsigned long)(BUS) << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ((unsigned long)(DEVFN) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ((unsigned long)(REG)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bus -= pbm->pci_first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return (void *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (SCHIZO_CONFIG_BASE(pbm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SCHIZO_CONFIG_ENCODE(bus, devfn, where));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* SCHIZO error handling support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum schizo_error_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static DEFINE_SPINLOCK(stc_buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static unsigned long stc_error_buf[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static unsigned long stc_tag_buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static unsigned long stc_line_buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCHIZO_STCERR_WRITE 0x2UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCHIZO_STCERR_READ 0x1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SCHIZO_STCTAG_READ 0x4000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum schizo_error_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct strbuf *strbuf = &pbm->stc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long regbase = pbm->pbm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long err_base, tag_base, line_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err_base = regbase + SCHIZO_STC_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tag_base = regbase + SCHIZO_STC_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) line_base = regbase + SCHIZO_STC_LINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock(&stc_buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* This is __REALLY__ dangerous. When we put the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * streaming buffer into diagnostic mode to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * it's tags and error status, we _must_ clear all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * of the line tag valid bits before re-enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * the streaming buffer. If any dirty data lives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * in the STC when we do this, we will end up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * invalidating it before it has a chance to reach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * main memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) control = upa_readq(strbuf->strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) strbuf->strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = upa_readq(err_base + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) upa_writeq(0UL, err_base + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) stc_error_buf[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) upa_writeq(0UL, tag_base + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) upa_writeq(0UL, line_base + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* OK, state is logged, exit diagnostic mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) upa_writeq(control, strbuf->strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int j, saw_error, first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) saw_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) first = i * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) last = first + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (j = first; j < last; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long errval = stc_error_buf[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (errval != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) saw_error++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (errval & SCHIZO_STCERR_READ) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (saw_error != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long tagval = stc_tag_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long lineval = stc_line_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) (tagval & SCHIZO_STCTAG_VPN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* XXX Should spit out per-bank error information... -DaveM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "V(%d)FOFN(%d)]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_unlock(&stc_buf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * controller level errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SCHIZO_IOMMU_TAG 0xa580UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SCHIZO_IOMMU_DATA 0xa600UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) enum schizo_error_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct iommu *iommu = pbm->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long iommu_tag[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long iommu_data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_lock_irqsave(&iommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) control = upa_readq(iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) char *type_string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Clear the error encountered bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) upa_writeq(control, iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) type_string = "Protection Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) type_string = "Invalid Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) type_string = "TimeOut Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) type_string = "ECC Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) printk("%s: IOMMU Error, type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pbm->name, type_string);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Put the IOMMU into diagnostic mode and probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * it's TLB for entries with error status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * It is very possible for another DVMA to occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * while we do this probe, and corrupt the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * further. But we are so screwed at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * that we are likely to crash hard anyways, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * get as much diagnostic information to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * console as we can.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) base = pbm->pbm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) iommu_tag[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) iommu_data[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Now clear out the entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Leave diagnostic mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) upa_writeq(control, iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long tag, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tag = iommu_tag[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!(tag & SCHIZO_IOMMU_TAG_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data = iommu_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) type_string = "Protection Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) type_string = "Invalid Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) type_string = "TimeOut Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) type_string = "ECC Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "sz(%dK) vpg(%08lx)]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pbm->name, i, type_string,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pbm->name, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (pbm->stc.strbuf_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) __schizo_check_stc_error_pbm(pbm, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) spin_unlock_irqrestore(&iommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) enum schizo_error_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) schizo_check_iommu_error_pbm(pbm, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (pbm->sibling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) schizo_check_iommu_error_pbm(pbm->sibling, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Uncorrectable ECC error status gathering. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SCHIZO_UE_AFSR 0x10030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SCHIZO_UE_AFAR 0x10038UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int reported, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Latch uncorrectable error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* If either of the error pending bits are set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * AFSR, the error status is being actively updated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * the hardware and we must re-read to get a clean value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) limit = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Clear the primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) printk("%s: Uncorrectable Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (((error_bits & SCHIZO_UEAFSR_PPIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "PIO" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ((error_bits & SCHIZO_UEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "DMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ((error_bits & SCHIZO_UEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "DMA Write" : "???")))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) printk("%s: UE Secondary errors [", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (afsr & SCHIZO_UEAFSR_SPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) printk("(PIO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (afsr & SCHIZO_UEAFSR_SDMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) printk("(DMA)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Interrogate IOMMU for error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) schizo_check_iommu_error(pbm, UE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SCHIZO_CE_AFSR 0x10040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SCHIZO_CE_AFAR 0x10048UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int reported, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Latch error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* If either of the error pending bits are set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * AFSR, the error status is being actively updated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * the hardware and we must re-read to get a clean value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) limit = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) printk("%s: Correctable Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (((error_bits & SCHIZO_CEAFSR_PPIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "PIO" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ((error_bits & SCHIZO_CEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "DMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ((error_bits & SCHIZO_CEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "DMA Write" : "???")))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* XXX Use syndrome and afar to print out module string just like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * XXX UDB CE trap handler does... -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) printk("%s: CE Secondary errors [", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (afsr & SCHIZO_CEAFSR_SPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) printk("(PIO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (afsr & SCHIZO_CEAFSR_SDMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) printk("(DMA)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SCHIZO_PCI_AFSR 0x2010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SCHIZO_PCI_AFAR 0x2018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SCHIZO_PCI_CTRL (0x2000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned long csr_reg, csr, csr_error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) csr = upa_readq(csr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) csr_error_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) csr & (SCHIZO_PCICTRL_BUS_UNUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SCHIZO_PCICTRL_TTO_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SCHIZO_PCICTRL_RTRY_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SCHIZO_PCICTRL_DTO_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SCHIZO_PCICTRL_SBH_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SCHIZO_PCICTRL_SERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (csr_error_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Clear the errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) upa_writeq(csr, csr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Log 'em. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) printk("%s: Bus unusable error asserted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) printk("%s: PCI TRDY# timeout error asserted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) printk("%s: PCI excessive retry error asserted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) printk("%s: PCI discard timeout error asserted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) printk("%s: PCI streaming byte hole error asserted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (csr_error_bits & SCHIZO_PCICTRL_SERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) printk("%s: PCI SERR signal asserted.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (stat & (PCI_STATUS_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PCI_STATUS_SIG_TARGET_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PCI_STATUS_REC_TARGET_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PCI_STATUS_REC_MASTER_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PCI_STATUS_SIG_SYSTEM_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pbm->name, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned long afsr_reg, afar_reg, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int reported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) base = pbm->pbm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) afsr_reg = base + SCHIZO_PCI_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) afar_reg = base + SCHIZO_PCI_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Latch error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return schizo_pcierr_intr_other(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) printk("%s: PCI Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) (((error_bits & SCHIZO_PCIAFSR_PMA) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "Master Abort" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ((error_bits & SCHIZO_PCIAFSR_PTA) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "Target Abort" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "Excessive Retries" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "Parity Error" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "Timeout" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "Bus Unusable" : "???"))))))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ((afsr & SCHIZO_PCIAFSR_CFG) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "Config" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ((afsr & SCHIZO_PCIAFSR_MEM) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "Memory" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ((afsr & SCHIZO_PCIAFSR_IO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "I/O" : "???"))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) printk("%s: PCI AFAR [%016lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) printk("%s: PCI Secondary errors [",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (afsr & SCHIZO_PCIAFSR_SMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) printk("(Master Abort)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (afsr & SCHIZO_PCIAFSR_STA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) printk("(Target Abort)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (afsr & SCHIZO_PCIAFSR_SRTRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) printk("(Excessive Retries)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (afsr & SCHIZO_PCIAFSR_SPERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) printk("(Parity Error)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (afsr & SCHIZO_PCIAFSR_STTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) printk("(Timeout)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (afsr & SCHIZO_PCIAFSR_SUNUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) printk("(Bus Unusable)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* For the error types shown, scan PBM's PCI bus for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * which have logged that error type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* If we see a Target Abort, this could be the result of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * IOMMU translation error of some sort. It is extremely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * useful to log this information as usually it indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * a bug in the IOMMU support code or a PCI device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) schizo_check_iommu_error(pbm, PCI_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pci_scan_for_target_abort(pbm, pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) pci_scan_for_master_abort(pbm, pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* For excessive retries, PSYCHO/PBM will abort the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * and there is no way to specifically check for excessive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * retries in the config space status registers. So what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * we hope is that we'll catch it via the master/target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * abort events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pci_scan_for_parity_error(pbm, pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SCHIZO_SAFARI_ERRLOG 0x10018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* We only expect UNMAP errors here. The rest of the Safari errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * are marked fatal and thus cause a system reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u64 errlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!(errlog & BUS_ERROR_UNMAP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pbm->name, errlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) schizo_check_iommu_error(pbm, SAFARI_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Nearly identical to PSYCHO equivalents... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define SCHIZO_ECC_CTRL 0x10020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ino &= IMAP_INO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (pbm->ino_bitmap & (1UL << ino))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* How the Tomatillo IRQs are routed around is pure guesswork here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * All the Tomatillo devices I see in prtconf dumps seem to have only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * a single PCI bus unit attached to it. It would seem they are separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * devices because their PortID (ie. JBUS ID) values are all different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * and thus the registers are mapped to totally different locations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * However, two Tomatillo's look "similar" in that the only difference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * in their PortID is the lowest bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * So if we were to ignore this lower bit, it certainly looks like two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * PCI bus units of the same Tomatillo. I still have not really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * figured this out...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u64 tmp, err_mask, err_no_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Tomatillo IRQ property layout is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * 0: PCIERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * 1: UE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * 2: CE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * 3: SERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * 4: POWER FAIL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "TOMATILLO_UE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) printk(KERN_WARNING "%s: Could not register UE, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "TOMATILLO_CE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) printk(KERN_WARNING "%s: Could not register CE, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "TOMATILLO_PCIERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "TOMATILLO_PCIERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) printk(KERN_WARNING "%s: Could not register PCIERR, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "TOMATILLO_SERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) printk(KERN_WARNING "%s: Could not register SERR, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Enable UE and CE interrupts for controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) upa_writeq((SCHIZO_ECCCTRL_EE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) SCHIZO_ECCCTRL_UE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Enable PCI Error interrupts and clear error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SCHIZO_PCICTRL_TTO_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SCHIZO_PCICTRL_RTRY_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SCHIZO_PCICTRL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SCHIZO_PCICTRL_EEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tmp |= err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) tmp &= ~err_no_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SCHIZO_PCIAFSR_PTTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SCHIZO_PCIAFSR_STTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) BUS_ERROR_APERR | BUS_ERROR_UNMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u64 tmp, err_mask, err_no_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Schizo IRQ property layout is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * 0: PCIERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * 1: UE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * 2: CE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * 3: SERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * 4: POWER FAIL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "SCHIZO_UE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) printk(KERN_WARNING "%s: Could not register UE, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "SCHIZO_CE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) printk(KERN_WARNING "%s: Could not register CE, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "SCHIZO_PCIERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "SCHIZO_PCIERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) printk(KERN_WARNING "%s: Could not register PCIERR, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "SCHIZO_SERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) printk(KERN_WARNING "%s: Could not register SERR, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Enable UE and CE interrupts for controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) upa_writeq((SCHIZO_ECCCTRL_EE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SCHIZO_ECCCTRL_UE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) SCHIZO_PCICTRL_ESLCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) SCHIZO_PCICTRL_TTO_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) SCHIZO_PCICTRL_RTRY_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) SCHIZO_PCICTRL_SBH_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) SCHIZO_PCICTRL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) SCHIZO_PCICTRL_EEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) SCHIZO_PCICTRL_SBH_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* Enable PCI Error interrupts and clear error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * bits for each PBM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) tmp |= err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) tmp &= ~err_no_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pbm->pbm_regs + SCHIZO_PCI_AFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* Make all Safari error conditions fatal except unmapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * errors which we make generate interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) BUS_ERROR_BADMA | BUS_ERROR_BADMB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) BUS_ERROR_BADMC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) BUS_ERROR_CIQTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) BUS_ERROR_ILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* XXX Something wrong with some Excalibur systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * XXX Sun is shipping. The behavior on a 2-cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * XXX machine is that both CPU1 parity error bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * XXX are set and are immediately set again when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * XXX their error status bits are cleared. Just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * XXX ignore them for now. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static void pbm_config_busmastering(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u8 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Set cache-line size to 64 bytes, this is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * a nop but I do it for completeness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) 0, PCI_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pci_config_write8(addr, 64 / sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Set PBM latency timer to 64 PCI clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) 0, PCI_LATENCY_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) pci_config_write8(addr, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pbm_config_busmastering(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pbm->is_66mhz_capable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) tomatillo_register_error_handlers(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) schizo_register_error_handlers(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define SCHIZO_STRBUF_CONTROL (0x02800UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define SCHIZO_STRBUF_FLUSH (0x02808UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define SCHIZO_STRBUF_FSYNC (0x02810UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) unsigned long base = pbm->pbm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* TOMATILLO lacks streaming cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* SCHIZO has context flushing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) pbm->stc.strbuf_flushflag = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ((((unsigned long)&pbm->stc.__flushflag_buf[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) + 63UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) & ~63UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pbm->stc.strbuf_flushflag_pa = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) __pa(pbm->stc.strbuf_flushflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Turn off LRU locking and diag mode, enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * streaming buffer and leave the rerun-disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * setting however OBP set it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) control = upa_readq(pbm->stc.strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) SCHIZO_STRBUF_CTRL_LENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) SCHIZO_STRBUF_CTRL_DENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) control |= SCHIZO_STRBUF_CTRL_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) upa_writeq(control, pbm->stc.strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) pbm->stc.strbuf_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define SCHIZO_IOMMU_CONTROL (0x00200UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define SCHIZO_IOMMU_FLUSH (0x00210UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) unsigned long i, tagbase, database;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct iommu *iommu = pbm->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int tsbsize, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) const u32 *vdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) u32 dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!vdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) vdma = vdma_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dma_mask = vdma[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) switch (vdma[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) case 0x20000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dma_mask |= 0x1fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) tsbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) case 0x40000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dma_mask |= 0x3fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) tsbsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) case 0x80000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dma_mask |= 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) tsbsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) printk(KERN_ERR PFX "Strange virtual-dma size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* Register addresses, SCHIZO has iommu ctx flushing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* We use the main control/status register of SCHIZO as the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * completion register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * Invalidate TLB Entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) control = upa_readq(iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) control |= SCHIZO_IOMMU_CTRL_DENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) upa_writeq(control, iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* Leave diag mode enabled for full-flushing done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * in pci_iommu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pbm->numa_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) control = upa_readq(iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) switch (tsbsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) control |= SCHIZO_IOMMU_TSBSZ_64K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) control |= SCHIZO_IOMMU_TSBSZ_128K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) control |= SCHIZO_IOMMU_CTRL_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) upa_writeq(control, iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define SCHIZO_IRQ_RETRY_INF 0xffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define SCHIZO_PCI_DIAG (0x2020UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Enable arbiter for all PCI slots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) tmp |= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pbm->chip_version >= 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) tmp |= SCHIZO_PCICTRL_PARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) tmp &= ~SCHIZO_PCICTRL_PARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) pbm->chip_version <= 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) tmp |= SCHIZO_PCICTRL_DTO_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) tmp &= ~SCHIZO_PCICTRL_DTO_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) tmp |= (SCHIZO_PCICTRL_MRM_PREF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SCHIZO_PCICTRL_RDO_PREF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) SCHIZO_PCICTRL_RDL_PREF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) SCHIZO_PCIDIAG_D_RETRY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) SCHIZO_PCIDIAG_D_INTSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* Clear prefetch lengths to workaround a bug in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * Jalapeno...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) tmp = (TOMATILLO_IOC_PART_WPENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) TOMATILLO_IOC_RDMULT_CPENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) TOMATILLO_IOC_RDONE_CPENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) TOMATILLO_IOC_RDLINE_CPENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int schizo_pbm_init(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct platform_device *op, u32 portid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) const struct linux_prom64_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) const char *chipset_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) switch (chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) case PBM_CHIP_TYPE_TOMATILLO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) chipset_name = "TOMATILLO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) case PBM_CHIP_TYPE_SCHIZO_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) chipset_name = "SCHIZO+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case PBM_CHIP_TYPE_SCHIZO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) chipset_name = "SCHIZO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* For SCHIZO, three OBP regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * 1) PBM controller regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * 2) Schizo front-end controller regs (same for both PBMs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * 3) PBM PCI config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * For TOMATILLO, four OBP regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * 1) PBM controller regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * 2) Tomatillo front-end controller regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * 3) PBM PCI config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * 4) Ichip regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) regs = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) pbm->next = pci_pbm_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) pci_pbm_root = pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) pbm->numa_node = NUMA_NO_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pbm->pci_ops = &sun4u_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) pbm->config_space_reg_bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pbm->index = pci_num_pbms++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pbm->portid = portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) pbm->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pbm->chip_type = chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pbm->chip_version = of_getintprop_default(dp, "version#", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pbm->pbm_regs = regs[0].phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pbm->name = dp->full_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) printk("%s: %s PCI Bus Module ver[%x:%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) pbm->name, chipset_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pbm->chip_version, pbm->chip_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) schizo_pbm_hw_init(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) pci_determine_mem_io_space(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pci_get_pbm_props(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) err = schizo_pbm_iommu_init(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) schizo_pbm_strbuf_init(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) schizo_scan_bus(pbm, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static inline int portid_compare(u32 x, u32 y, int chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (x == (y ^ 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return (x == y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (portid_compare(pbm->portid, portid, chip_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static int __schizo_init(struct platform_device *op, unsigned long chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) portid = of_getintprop_default(dp, "portid", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (!pbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) pbm->sibling = schizo_find_sibling(portid, chip_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (!iommu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto out_free_pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) pbm->iommu = iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (schizo_pbm_init(pbm, op, portid, chip_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (pbm->sibling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pbm->sibling->sibling = pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dev_set_drvdata(&op->dev, pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) out_free_iommu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) kfree(pbm->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) out_free_pbm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) kfree(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static const struct of_device_id schizo_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static int schizo_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) match = of_match_device(schizo_match, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return __schizo_init(op, (unsigned long)match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* The ordering of this table is very important. Some Tomatillo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * nodes announce that they are compatible with both pci108e,a801
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * and pci108e,8001. So list the chips in reverse chronological
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const struct of_device_id schizo_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .compatible = "pci108e,a801",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .compatible = "pci108e,8002",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .compatible = "pci108e,8001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .data = (void *) PBM_CHIP_TYPE_SCHIZO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static struct platform_driver schizo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .of_match_table = schizo_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .probe = schizo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static int __init schizo_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return platform_driver_register(&schizo_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) subsys_initcall(schizo_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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