^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pci_sabre.c: Sabre specific PCI controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/apb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/upa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "iommu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "psycho_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_NAME "sabre"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PFX DRIVER_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* SABRE PCI controller register offsets and definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SABRE_UE_AFSR 0x0030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SABRE_UECE_AFAR 0x0038UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SABRE_CE_AFSR 0x0040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SABRE_IOMMU_CONTROL 0x0200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SABRE_IOMMU_TSBBASE 0x0208UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SABRE_IOMMU_FLUSH 0x0210UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SABRE_IMAP_A_SLOT0 0x0c00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SABRE_IMAP_B_SLOT0 0x0c20UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SABRE_IMAP_SCSI 0x1000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SABRE_IMAP_ETH 0x1008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SABRE_IMAP_BPP 0x1010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SABRE_IMAP_AU_REC 0x1018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SABRE_IMAP_AU_PLAY 0x1020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SABRE_IMAP_PFAIL 0x1028UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SABRE_IMAP_KMS 0x1030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SABRE_IMAP_FLPY 0x1038UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SABRE_IMAP_SHW 0x1040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SABRE_IMAP_KBD 0x1048UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SABRE_IMAP_MS 0x1050UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SABRE_IMAP_SER 0x1058UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SABRE_IMAP_UE 0x1070UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SABRE_IMAP_CE 0x1078UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SABRE_IMAP_PCIERR 0x1080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SABRE_IMAP_GFX 0x1098UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SABRE_IMAP_EUPA 0x10a0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SABRE_ICLR_A_SLOT0 0x1400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SABRE_ICLR_B_SLOT0 0x1480UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SABRE_ICLR_SCSI 0x1800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SABRE_ICLR_ETH 0x1808UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SABRE_ICLR_BPP 0x1810UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SABRE_ICLR_AU_REC 0x1818UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SABRE_ICLR_AU_PLAY 0x1820UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SABRE_ICLR_PFAIL 0x1828UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SABRE_ICLR_KMS 0x1830UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SABRE_ICLR_FLPY 0x1838UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SABRE_ICLR_SHW 0x1840UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SABRE_ICLR_KBD 0x1848UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SABRE_ICLR_MS 0x1850UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SABRE_ICLR_SER 0x1858UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SABRE_ICLR_UE 0x1870UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SABRE_ICLR_CE 0x1878UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SABRE_ICLR_PCIERR 0x1880UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SABRE_WRSYNC 0x1c20UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SABRE_PCICTRL 0x2000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SABRE_PIOAFSR 0x2010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SABRE_PIOAFAR 0x2018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SABRE_PCIDIAG 0x2020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SABRE_PCITASR 0x2028UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SABRE_PIOBUF_DIAG 0x5000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SABRE_DMABUF_DIAGLO 0x5100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SABRE_DMABUF_DIAGHI 0x51c0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SABRE_IOMMU_VADIAG 0xa400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SABRE_IOMMU_TCDIAG 0xa408UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SABRE_IOMMU_TAG 0xa580UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SABRE_IOMMU_DATA 0xa600UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SABRE_PCI_IRQSTATE 0xa800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SABRE_OBIO_IRQSTATE 0xa808UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SABRE_FFBCFG 0xf000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SABRE_MCCTRL0 0xf010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SABRE_MCCTRL1 0xf018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SABRE_RESETCTRL 0xf020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SABRE_CONFIGSPACE 0x001000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SABRE_IOSPACE 0x002000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SABRE_IOSPACE_SIZE 0x000ffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SABRE_MEMSPACE 0x100000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int hummingbird_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct pci_bus *sabre_root_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int reported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Latch uncorrectable error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Clear the primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ((error_bits & SABRE_UEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "DMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ((error_bits & SABRE_UEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "DMA Write" : "???")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ((error_bits & SABRE_UEAFSR_PDTE) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ":Translation Error" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (afsr & SABRE_UEAFSR_OFF) >> 29UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) printk("%s: UE Secondary errors [", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (afsr & SABRE_UEAFSR_SDRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) printk("(DMA Read)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (afsr & SABRE_UEAFSR_SDWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) printk("(DMA Write)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (afsr & SABRE_UEAFSR_SDTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) printk("(Translation Error)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Interrogate IOMMU for error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int reported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Latch error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) printk("%s: Correctable Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ((error_bits & SABRE_CEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "DMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ((error_bits & SABRE_CEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "DMA Write" : "???")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* XXX Use syndrome and afar to print out module string just like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * XXX UDB CE trap handler does... -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "was_block(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) (afsr & SABRE_CEAFSR_OFF) >> 29UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) printk("%s: CE Secondary errors [", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (afsr & SABRE_CEAFSR_SDRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) printk("(DMA Read)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (afsr & SABRE_CEAFSR_SDWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) printk("(DMA Write)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct device_node *dp = pbm->op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long base = pbm->controller_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dp = dp->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) op = of_find_device_by_node(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Sabre/Hummingbird IRQ property layout is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 0: PCI ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 1: UE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * 2: CE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * 3: POWER FAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (op->archdata.num_irqs < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* We clear the error bits in the appropriate AFSR before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * registering the handler so that we don't get spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) base + SABRE_UE_AFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) base + SABRE_CE_AFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "SABRE_PCIERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) tmp = upa_readq(base + SABRE_PCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tmp |= SABRE_PCICTRL_ERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) upa_writeq(tmp, base + SABRE_PCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void apb_init(struct pci_bus *sabre_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (pdev->vendor == PCI_VENDOR_ID_SUN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 word16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pci_read_config_word(pdev, PCI_COMMAND, &word16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PCI_COMMAND_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pci_write_config_word(pdev, PCI_COMMAND, word16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Status register bits are "write 1 to clear". */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pci_write_config_word(pdev, PCI_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Use a primary/seconday latency timer value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * of 64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Enable reporting/forwarding of master aborts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * parity, and SERR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) (PCI_BRIDGE_CTL_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PCI_BRIDGE_CTL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PCI_BRIDGE_CTL_MASTER_ABORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int once;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* The APB bridge speaks to the Sabre host PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * at 66Mhz, but the front side of APB runs at 33Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * for both segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Hummingbird systems do not use APB, so they run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * at 66MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (hummingbird_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pbm->is_66mhz_capable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pbm->is_66mhz_capable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* This driver has not been verified to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * multiple SABREs yet, so trap this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Also note that the SABRE host bridge is hardwired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * to live at bus 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (once != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) once++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!pbm->pci_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sabre_root_bus = pbm->pci_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) apb_init(pbm->pci_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sabre_register_error_handlers(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void sabre_pbm_init(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sabre_scan_bus(pbm, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct of_device_id sabre_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int sabre_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) const struct linux_prom64_registers *pr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 upa_portid, dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int tsbsize, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const u32 *vdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u64 clear_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) match = of_match_device(sabre_match, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) hummingbird_p = match && (match->data != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!hummingbird_p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct device_node *cpu_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Of course, Sun has to encode things a thousand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * different ways, inconsistently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for_each_node_by_type(cpu_dp, "cpu") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (of_node_name_eq(cpu_dp, "SUNW,UltraSPARC-IIe"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hummingbird_p = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!pbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!iommu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) goto out_free_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pbm->iommu = iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pbm->portid = upa_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Map in SABRE register set and report the presence of this SABRE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pr_regs = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!pr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) printk(KERN_ERR PFX "No reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * First REG in property is base of entire SABRE register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pbm->controller_regs = pr_regs[0].phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* PCI first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Then OBIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Error interrupts are enabled later after the bus scan. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pbm->controller_regs + SABRE_PCICTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Now map in PCI config space for entire SABRE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) vdma = of_get_property(dp, "virtual-dma", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!vdma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) printk(KERN_ERR PFX "No virtual-dma property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dma_mask = vdma[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) switch(vdma[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case 0x20000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dma_mask |= 0x1fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) tsbsize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case 0x40000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dma_mask |= 0x3fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) tsbsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case 0x80000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dma_mask |= 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) tsbsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) printk(KERN_ERR PFX "Strange virtual-dma size.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Look for APB underneath.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sabre_pbm_init(pbm, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pbm->next = pci_pbm_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pci_pbm_root = pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_set_drvdata(&op->dev, pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) out_free_iommu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) kfree(pbm->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) out_free_controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) kfree(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const struct of_device_id sabre_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .compatible = "pci108e,a001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .data = (void *) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .compatible = "pci108e,a000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static struct platform_driver sabre_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .of_match_table = sabre_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .probe = sabre_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int __init sabre_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return platform_driver_register(&sabre_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) subsys_initcall(sabre_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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