^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/starfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/upa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "iommu_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "psycho_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_NAME "psycho"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PFX DRIVER_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Misc. PSYCHO PCI controller register offsets and definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PSYCHO_CONTROL 0x0010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PSYCHO_PCIA_CTRL 0x2000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PSYCHO_PCIB_CTRL 0x4000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* PSYCHO error handling support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Helper function of IOMMU error checking, which checks out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * the state of the streaming buffers. The IOMMU lock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * held when this is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * For the PCI error case we know which PBM (and thus which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * streaming buffer) caused the error, but for the uncorrectable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * error case we do not. So we always check both streaming caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PSYCHO_STC_DATA_A 0xb000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PSYCHO_STC_DATA_B 0xc000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PSYCHO_STC_ERR_A 0xb400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PSYCHO_STC_ERR_B 0xc400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PSYCHO_STC_TAG_A 0xb800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PSYCHO_STC_TAG_B 0xc800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PSYCHO_STC_LINE_A 0xb900UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PSYCHO_STC_LINE_B 0xc900UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* When an Uncorrectable Error or a PCI Error happens, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * interrogate the IOMMU state to see if it is the cause.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PSYCHO_IOMMU_CONTROL 0x0200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PSYCHO_IOMMU_TSBBASE 0x0208UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PSYCHO_IOMMU_FLUSH 0x0210UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PSYCHO_IOMMU_TAG 0xa580UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PSYCHO_IOMMU_DATA 0xa600UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Uncorrectable Errors. Cause of the error and the address are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * relating to UPA interface transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PSYCHO_UE_AFSR 0x0030UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PSYCHO_UE_AFAR 0x0038UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int reported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Latch uncorrectable error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Clear the primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) printk("%s: Uncorrectable Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (((error_bits & PSYCHO_UEAFSR_PPIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "PIO" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ((error_bits & PSYCHO_UEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "DMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ((error_bits & PSYCHO_UEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "DMA Write" : "???")))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) printk("%s: UE Secondary errors [", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (afsr & PSYCHO_UEAFSR_SPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) printk("(PIO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (afsr & PSYCHO_UEAFSR_SDRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) printk("(DMA Read)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (afsr & PSYCHO_UEAFSR_SDWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) printk("(DMA Write)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Interrogate both IOMMUs for error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pbm->sibling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Correctable Errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PSYCHO_CE_AFSR 0x0040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PSYCHO_CE_AFAR 0x0040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct pci_pbm_info *pbm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long afsr, afar, error_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int reported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Latch error status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) afar = upa_readq(afar_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) afsr = upa_readq(afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Clear primary/secondary error status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) error_bits = afsr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!error_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) upa_writeq(error_bits, afsr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Log the error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) printk("%s: Correctable Error, primary error type[%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (((error_bits & PSYCHO_CEAFSR_PPIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "PIO" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ((error_bits & PSYCHO_CEAFSR_PDRD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "DMA Read" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ((error_bits & PSYCHO_CEAFSR_PDWR) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "DMA Write" : "???")))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* XXX Use syndrome and afar to print out module string just like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * XXX UDB CE trap handler does... -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "UPA_MID[%02lx] was_block(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pbm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) printk("%s: CE Secondary errors [", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reported = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (afsr & PSYCHO_CEAFSR_SPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) printk("(PIO)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (afsr & PSYCHO_CEAFSR_SDRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) printk("(DMA Read)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (afsr & PSYCHO_CEAFSR_SDWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reported++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) printk("(DMA Write)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!reported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) printk("(none)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) printk("]\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* PCI Errors. They are signalled by the PCI bus module since they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * are associated with a specific bus segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PSYCHO_PCI_AFSR_A 0x2010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PSYCHO_PCI_AFSR_B 0x4010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PSYCHO_PCI_AFAR_A 0x2018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PSYCHO_PCI_AFAR_B 0x4018UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* XXX What about PowerFail/PowerManagement??? -DaveM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PSYCHO_ECC_CTRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long base = pbm->controller_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Psycho interrupt property order is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * 0: PCIERR INO for this PBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * 1: UE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * 2: CE ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 3: POWER FAIL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * 4: SPARE HARDWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * 5: POWER MANAGEMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (op->archdata.num_irqs < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* We really mean to ignore the return result here. Two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * PCI controller share the same interrupt numbers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * drive the same front-end hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "PSYCHO_UE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "PSYCHO_CE", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* This one, however, ought not to fail. We can just warn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * about it since the system can still operate properly even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * if this fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "PSYCHO_PCIERR", pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) printk(KERN_WARNING "%s: Could not register PCIERR, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "err=%d\n", pbm->name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Enable UE and CE interrupts for controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) upa_writeq((PSYCHO_ECCCTRL_EE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PSYCHO_ECCCTRL_UE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Enable PCI Error interrupts and clear error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * bits for each PBM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tmp = upa_readq(base + PSYCHO_PCIA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tmp |= (PSYCHO_PCICTRL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PSYCHO_PCICTRL_SBH_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PSYCHO_PCICTRL_EEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) upa_writeq(tmp, base + PSYCHO_PCIA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tmp = upa_readq(base + PSYCHO_PCIB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tmp |= (PSYCHO_PCICTRL_SERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PSYCHO_PCICTRL_SBH_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PSYCHO_PCICTRL_EEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) upa_writeq(tmp, base + PSYCHO_PCIB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* PSYCHO boot time probing and initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void pbm_config_busmastering(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Set cache-line size to 64 bytes, this is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * a nop but I do it for completeness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0, PCI_CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pci_config_write8(addr, 64 / sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Set PBM latency timer to 64 PCI clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0, PCI_LATENCY_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pci_config_write8(addr, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void psycho_scan_bus(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pbm_config_busmastering(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pbm->is_66mhz_capable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* After the PCI bus scan is complete, we can register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * the error interrupt handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) psycho_register_error_handlers(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PSYCHO_IRQ_RETRY 0x1a00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PSYCHO_PCIA_DIAG 0x2020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PSYCHO_PCIB_DIAG 0x4020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Enable arbiter for all PCI slots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tmp |= PSYCHO_PCICTRL_AEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tmp |= PSYCHO_PCICTRL_AEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Disable DMA write / PIO read synchronization on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * both PCI bus segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * [ U2P Erratum 1243770, STP2223BGA data sheet ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tmp |= PSYCHO_PCIDIAG_DDWSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tmp |= PSYCHO_PCIDIAG_DDWSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int is_pbm_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long base = pbm->controller_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (is_pbm_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* PSYCHO's streaming buffer lacks ctx flushing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pbm->stc.strbuf_ctxflush = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pbm->stc.strbuf_ctxmatch_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pbm->stc.strbuf_flushflag = (volatile unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ((((unsigned long)&pbm->stc.__flushflag_buf[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) + 63UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) & ~63UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pbm->stc.strbuf_flushflag_pa = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) __pa(pbm->stc.strbuf_flushflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Enable the streaming buffer. We have to be careful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * just in case OBP left it with LRU locking enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * It is possible to control if PBM will be rerun on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * line misses. Currently I just retain whatever setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * OBP left us with. All checks so far show it having
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * a value of zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #undef PSYCHO_STRBUF_RERUN_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #undef PSYCHO_STRBUF_RERUN_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) control = upa_readq(pbm->stc.strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) control |= PSYCHO_STRBUF_CTRL_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #ifdef PSYCHO_STRBUF_RERUN_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef PSYCHO_STRBUF_RERUN_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) control |= PSYCHO_STRBUF_CTRL_RRDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) upa_writeq(control, pbm->stc.strbuf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pbm->stc.strbuf_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define PSYCHO_IOSPACE_A 0x002000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define PSYCHO_IOSPACE_B 0x002010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define PSYCHO_MEMSPACE_A 0x100000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define PSYCHO_MEMSPACE_B 0x180000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void psycho_pbm_init(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct platform_device *op, int is_pbm_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) psycho_pbm_strbuf_init(pbm, is_pbm_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) psycho_scan_bus(pbm, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pbm->portid == upa_portid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PSYCHO_CONFIGSPACE 0x001000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int psycho_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) const struct linux_prom64_registers *pr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int is_pbm_a, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 upa_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!pbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pbm->sibling = psycho_find_sibling(upa_portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (pbm->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) iommu = pbm->sibling->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!iommu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto out_free_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pbm->iommu = iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pbm->portid = upa_portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pr_regs = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!pr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) printk(KERN_ERR PFX "No reg property.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pbm->controller_regs = pr_regs[2].phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (is_pbm_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) psycho_controller_hwinit(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!pbm->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) err = psycho_iommu_init(pbm, 128, 0xc0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0xffffffff, PSYCHO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* If necessary, hook us up for starfire IRQ translations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (this_is_starfire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) starfire_hookup(pbm->portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) psycho_pbm_init(pbm, op, is_pbm_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pbm->next = pci_pbm_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pci_pbm_root = pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (pbm->sibling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pbm->sibling->sibling = pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_set_drvdata(&op->dev, pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) out_free_iommu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!pbm->sibling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) kfree(pbm->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) out_free_controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) kfree(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct of_device_id psycho_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .compatible = "pci108e,8000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct platform_driver psycho_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .of_match_table = psycho_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .probe = psycho_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int __init psycho_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return platform_driver_register(&psycho_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) subsys_initcall(psycho_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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