^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pci_impl.h: Helper definitions for PCI controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef PCI_IMPL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PCI_IMPL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* The abstraction used here is that there are PCI controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * underneath. Each PCI bus module uses an IOMMU (shared by both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * PBMs of a controller, or per-PBM), and if a streaming buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * is present, each PCI bus module has it's own. (ie. the IOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * might be shared between PBMs, the STC is never shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Furthermore, each PCI bus module controls it's own autonomous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * PCI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_STC_FLUSHFLAG_INIT(STC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) (*((STC)->strbuf_flushflag) = 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_STC_FLUSHFLAG_SET(STC) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (*((STC)->strbuf_flushflag) != 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pci_pbm_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct sparc64_msiq_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long *head, unsigned long *msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long msi, int is_msi64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int (*msiq_alloc)(struct pci_pbm_info *pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void (*msiq_free)(struct pci_pbm_info *pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void sparc64_pbm_msi_init(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct sparc64_msiq_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct sparc64_msiq_cookie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long msiqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct pci_pbm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pci_pbm_info *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pci_pbm_info *sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Physical address base of controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long controller_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Physical address base of PBM registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long pbm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Physical address of DMA sync register, if any. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long sync_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Opaque 32-bit system bus Port ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Opaque 32-bit handle used for hypervisor calls. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 devhandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Chipset version information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PBM_CHIP_TYPE_SABRE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PBM_CHIP_TYPE_PSYCHO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PBM_CHIP_TYPE_SCHIZO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PBM_CHIP_TYPE_SCHIZO_PLUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PBM_CHIP_TYPE_TOMATILLO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int chip_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Name used for top-level resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* OBP specific information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u64 ino_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* PBM I/O and Memory space resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct resource io_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct resource mem_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct resource mem64_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct resource busn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) resource_size_t io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) resource_size_t mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) resource_size_t mem64_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Base of PCI Config space, can be per-PBM or shared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long config_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* This will be 12 on PCI-E controllers, 8 elsewhere. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long config_space_reg_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long pci_afsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long pci_afar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long pci_csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* State of 66MHz capabilities on this PBM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int is_66mhz_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int all_devs_66mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* MSI info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 msiq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 msiq_ent_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 msiq_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 msiq_first_devino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 msiq_rotor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct sparc64_msiq_cookie *msiq_irq_cookies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 msi_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 msi_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 msi_data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 msix_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u64 msi32_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u64 msi64_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 msi32_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 msi64_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void *msi_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long *msi_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int *msi_irq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct msi_desc *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct sparc64_msiq_ops *msi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif /* !(CONFIG_PCI_MSI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* This PBM's streaming buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct strbuf stc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* IOMMU state, potentially shared by both PBM segments. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Now things for the actual PCI bus probes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int pci_first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int pci_last_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pci_bus *pci_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pci_ops *pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int numa_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) extern struct pci_pbm_info *pci_pbm_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) extern int pci_num_pbms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* PCI bus scanning and fixup support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void pci_get_pbm_props(struct pci_pbm_info *pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct device *parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void pci_determine_mem_io_space(struct pci_pbm_info *pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Error reporting support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Configuration space access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void pci_config_read8(u8 *addr, u8 *ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void pci_config_read16(u16 *addr, u16 *ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void pci_config_read32(u32 *addr, u32 *ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void pci_config_write8(u8 *addr, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void pci_config_write16(u16 *addr, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void pci_config_write32(u32 *addr, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) extern struct pci_ops sun4u_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) extern struct pci_ops sun4v_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) extern volatile int pci_poke_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) extern volatile int pci_poke_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) extern volatile int pci_poke_faulted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif /* !(PCI_IMPL_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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