^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pci_fire.c: Sun4u platform PCI-E controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/numa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/upa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRIVER_NAME "fire"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PFX DRIVER_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FIRE_IOMMU_CONTROL 0x40000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FIRE_IOMMU_TSBBASE 0x40008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FIRE_IOMMU_FLUSH 0x40100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FIRE_IOMMU_FLUSHINV 0x40108UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct iommu *iommu = pbm->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 vdma[2], dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u64 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int tsbsize, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* No virtual-dma property on these guys, use largest size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) vdma[0] = 0xc0000000; /* base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) vdma[1] = 0x40000000; /* size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dma_mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) tsbsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Register addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* We use the main control/status register of FIRE as the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * completion register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Invalidate TLB Entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) upa_writeq(~(u64)0, iommu->iommu_flushinv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pbm->numa_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) control = upa_readq(iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) control |= (0x00000400 /* TSB cache snoop enable */ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x00000300 /* Cache mode */ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x00000002 /* Bypass enable */ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x00000001 /* Translation enable */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) upa_writeq(control, iommu->iommu_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pci_msiq_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u64 word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSIQ_WORD0_RESV 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSIQ_WORD0_FMT_TYPE_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MSIQ_WORD0_LEN 0x00ffc00000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MSIQ_WORD0_LEN_SHIFT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MSIQ_WORD0_ADDR0_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MSIQ_WORD0_RID 0x00000000ffff0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MSIQ_WORD0_RID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MSIQ_WORD0_DATA0 0x000000000000ffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MSIQ_WORD0_DATA0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MSIQ_TYPE_MSG 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSIQ_TYPE_MSI32 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSIQ_TYPE_MSI64 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u64 word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MSIQ_WORD1_ADDR1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSIQ_WORD1_DATA1 0x000000000000ffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MSIQ_WORD1_DATA1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 resv[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* All MSI registers are offset from pbm->pbm_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MSI_MAP_VALID 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MSI_MAP_EQWR_N 0x4000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MSI_MAP_EQNUM 0x000000000000003fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MSI_CLEAR_EQWR_N 0x4000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMONDO_DATA0 0x02C000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMONDO_DATA1 0x02C008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMONDO_DATA1_DATA 0xffffffffffffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MSI_32BIT_ADDR 0x034000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MSI_64BIT_ADDR 0x034008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long *head, unsigned long *msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long type_fmt, type, msi_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pci_msiq_entry *base, *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ep = &base[*head];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MSIQ_WORD0_FMT_TYPE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) type = (type_fmt >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (unlikely(type != MSIQ_TYPE_MSI32 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) type != MSIQ_TYPE_MSI64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MSIQ_WORD0_DATA0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Clear the entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Go to next entry in ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (*head)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (*head >= pbm->msiq_ent_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long msi, int is_msi64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val &= ~(MSI_MAP_EQNUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val |= msiqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val |= MSI_MAP_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val &= ~MSI_MAP_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long pages, order, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) order = get_order(512 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (pages == 0UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) memset((char *)pages, 0, PAGE_SIZE << order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pbm->msi_queues = (void *) pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __pa(pbm->msi_queues)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (i = 0; i < pbm->msiq_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long pages, order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) order = get_order(512 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pages = (unsigned long) pbm->msi_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) free_pages(pages, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pbm->msi_queues = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long msiqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long cregs = (unsigned long) pbm->pbm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long imap_reg, iclr_reg, int_ctrlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* XXX iterate amongst the 4 IRQ controllers XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int_ctrlr = (1UL << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val = upa_readq(imap_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val |= (1UL << 63) | int_ctrlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) upa_writeq(val, imap_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) irq = build_irq(fixup, iclr_reg, imap_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .get_head = pci_fire_get_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .dequeue_msi = pci_fire_dequeue_msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .set_head = pci_fire_set_head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .msi_setup = pci_fire_msi_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .msi_teardown = pci_fire_msi_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .msiq_alloc = pci_fire_msiq_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .msiq_free = pci_fire_msiq_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .msiq_build_irq = pci_fire_msiq_build_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void pci_fire_msi_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #else /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void pci_fire_msi_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #endif /* !(CONFIG_PCI_MSI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Based at pbm->controller_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define FIRE_PARITY_CONTROL 0x470010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define FIRE_PARITY_ENAB 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define FIRE_FATAL_RESET_CTL 0x471028UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define FIRE_FATAL_RESET_MB 0x0000000002000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define FIRE_FATAL_RESET_APE 0x0000000000004000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define FIRE_FATAL_RESET_JW 0x0000000000000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define FIRE_FATAL_RESET_JI 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define FIRE_FATAL_RESET_JR 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define FIRE_CORE_INTR_ENABLE 0x471800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Based at pbm->pbm_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define FIRE_TLU_CTRL 0x80000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define FIRE_TLU_DEV_CTRL 0x90008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define FIRE_TLU_LINK_CTRL 0x90020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define FIRE_LPU_RESET 0xe2008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define FIRE_LPU_LLCFG 0xe2200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define FIRE_LPU_TXL_FIFOP 0xe2430UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define FIRE_LPU_LTSSM_CFG2 0xe2788UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define FIRE_LPU_LTSSM_CFG3 0xe2790UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define FIRE_LPU_LTSSM_CFG4 0xe2798UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define FIRE_DMC_IENAB 0x31800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define FIRE_DMC_DBG_SEL_A 0x53000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define FIRE_DMC_DBG_SEL_B 0x53008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define FIRE_PEC_IENAB 0x51800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void pci_fire_hw_init(struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) upa_writeq(FIRE_PARITY_ENAB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pbm->controller_regs + FIRE_PARITY_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) upa_writeq((FIRE_FATAL_RESET_SPARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FIRE_FATAL_RESET_MB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) FIRE_FATAL_RESET_CPE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FIRE_FATAL_RESET_APE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FIRE_FATAL_RESET_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FIRE_FATAL_RESET_JW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FIRE_FATAL_RESET_JI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FIRE_FATAL_RESET_JR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pbm->controller_regs + FIRE_FATAL_RESET_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) val |= (FIRE_TLU_CTRL_TIM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FIRE_TLU_CTRL_QDET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FIRE_TLU_CTRL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) upa_writeq(((0xffff << 16) | (0x0000 << 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) upa_writeq((2 << 16) | (140 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int pci_fire_pbm_init(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct platform_device *op, u32 portid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) const struct linux_prom64_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pbm->numa_node = NUMA_NO_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pbm->pci_ops = &sun4u_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pbm->config_space_reg_bits = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pbm->index = pci_num_pbms++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pbm->portid = portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pbm->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pbm->name = dp->full_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) regs = of_get_property(dp, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pbm->pbm_regs = regs[0].phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pci_determine_mem_io_space(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pci_get_pbm_props(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pci_fire_hw_init(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) err = pci_fire_pbm_iommu_init(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pci_fire_msi_init(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* XXX register error interrupt handlers XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pbm->next = pci_pbm_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pci_pbm_root = pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int fire_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct pci_pbm_info *pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) portid = of_getintprop_default(dp, "portid", 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!pbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!iommu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto out_free_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pbm->iommu = iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err = pci_fire_pbm_init(pbm, op, portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) goto out_free_iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_set_drvdata(&op->dev, pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) out_free_iommu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) kfree(pbm->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) out_free_controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) kfree(pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct of_device_id fire_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .compatible = "pciex108e,80f0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct platform_driver fire_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .of_match_table = fire_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .probe = fire_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int __init fire_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return platform_driver_register(&fire_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) subsys_initcall(fire_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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