^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* pci.c: UltraSparc PCI controller support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * OF tree based PCI bus probing taken from the PowerPC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * with minor modifications, see there for credits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/capability.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/apb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pci_impl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* List of all PCI controllers found in the system. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pci_pbm_info *pci_pbm_root = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Each PBM found gets a unique index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int pci_num_pbms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) volatile int pci_poke_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) volatile int pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) volatile int pci_poke_faulted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static DEFINE_SPINLOCK(pci_poke_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void pci_config_read8(u8 *addr, u8 *ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) spin_lock_irqsave(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pci_poke_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pci_poke_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pci_poke_faulted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __asm__ __volatile__("membar #Sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "lduba [%1] %2, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) : "=r" (byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_poke_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!pci_poke_faulted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *ret = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) spin_unlock_irqrestore(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void pci_config_read16(u16 *addr, u16 *ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_lock_irqsave(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci_poke_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pci_poke_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_poke_faulted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __asm__ __volatile__("membar #Sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "lduha [%1] %2, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) : "=r" (word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pci_poke_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!pci_poke_faulted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *ret = word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) spin_unlock_irqrestore(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void pci_config_read32(u32 *addr, u32 *ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spin_lock_irqsave(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pci_poke_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pci_poke_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci_poke_faulted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __asm__ __volatile__("membar #Sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "lduwa [%1] %2, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) : "=r" (dword)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pci_poke_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!pci_poke_faulted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *ret = dword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) spin_unlock_irqrestore(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void pci_config_write8(u8 *addr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) spin_lock_irqsave(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pci_poke_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pci_poke_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pci_poke_faulted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __asm__ __volatile__("membar #Sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "stba %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_poke_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void pci_config_write16(u16 *addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spin_lock_irqsave(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pci_poke_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_poke_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pci_poke_faulted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __asm__ __volatile__("membar #Sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "stha %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pci_poke_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock_irqrestore(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void pci_config_write32(u32 *addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_lock_irqsave(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pci_poke_cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pci_poke_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pci_poke_faulted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __asm__ __volatile__("membar #Sync\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "stwa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pci_poke_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_poke_cpu = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spin_unlock_irqrestore(&pci_poke_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int ofpci_verbose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int __init ofpci_debug(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) get_option(&str, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ofpci_verbose = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __setup("ofpci_debug=", ofpci_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned long pci_parse_of_flags(u32 addr0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (addr0 & 0x02000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (addr0 & 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) flags |= IORESOURCE_MEM_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) | PCI_BASE_ADDRESS_MEM_TYPE_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (addr0 & 0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) flags |= IORESOURCE_PREFETCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) | PCI_BASE_ADDRESS_MEM_PREFETCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else if (addr0 & 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* The of_device layer has translated all of the assigned-address properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * into physical address resources, we only have to figure out the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void pci_parse_of_addrs(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct resource *op_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const u32 *addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int proplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) addrs = of_get_property(node, "assigned-addresses", &proplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!addrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_info(dev, " parse addresses (%d bytes) @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) proplen, addrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) op_res = &op->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) flags = pci_parse_of_flags(addrs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) i = addrs[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_info(dev, " start: %llx, end: %llx, i: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) op_res->start, op_res->end, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else if (i == dev->rom_base_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) res = &dev->resource[PCI_ROM_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci_err(dev, "bad cfg reg num 0x%x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) res->start = op_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) res->end = op_res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) res->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) res->name = pci_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pci_info(dev, "reg 0x%x: %pR\n", i, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void *stc, void *host_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int numa_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sd->iommu = iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sd->stc = stc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sd->host_controller = host_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sd->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sd->numa_node = numa_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct pci_bus *bus, int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct dev_archdata *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct platform_device *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev = pci_alloc_dev(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) op = of_find_device_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sd = &dev->dev.archdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pbm->numa_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) sd = &op->dev.archdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) sd->iommu = pbm->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sd->stc = &pbm->stc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sd->numa_node = pbm->numa_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (of_node_name_eq(node, "ebus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) of_propagate_archdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pci_info(bus," create device, devfn: %x, type: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) devfn, of_node_get_device_type(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev->sysdata = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev->dev.parent = bus->bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev->dev.bus = &pci_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev->dev.of_node = of_node_get(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev->devfn = devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev->multifunction = 0; /* maybe a lie? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) set_pcie_port_type(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_dev_assign_slot(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev->device = of_getintprop_default(node, "device-id", 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev->subsystem_vendor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) of_getintprop_default(node, "subsystem-vendor-id", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev->subsystem_device =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) of_getintprop_default(node, "subsystem-id", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev->cfg_size = pci_cfg_space_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* We can't actually use the firmware value, we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * to read what is in the register right now. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * reason is that in the case of IDE interfaces the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * firmware can sample the value before the the IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * interface is programmed into native mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev->class = class >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev->revision = class & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* I have seen IDE devices which will not respond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * the bmdma simplex check reads if bus mastering is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev->current_state = PCI_UNKNOWN; /* unknown power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev->error_state = pci_channel_io_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev->dma_mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (of_node_name_eq(node, "pci")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* a PCI-PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev->rom_base_reg = PCI_ROM_ADDRESS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else if (of_node_is_type(node, "cardbus")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev->rom_base_reg = PCI_ROM_ADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev->irq = sd->op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (dev->irq == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev->irq = PCI_IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev->vendor, dev->device, dev->hdr_type, dev->class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pci_parse_of_addrs(sd->op, node, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pci_info(dev, " adding to system ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pci_device_add(dev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 idx, first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) first = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) last = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (idx = 0; idx < 8; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if ((map & (1 << idx)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (first > idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) first = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (last < idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) last = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *first_p = first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *last_p = last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * a proper 'ranges' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void apb_fake_ranges(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct pci_pbm_info *pbm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 first, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) apb_calc_first_last(map, &first, &last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) res = bus->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) res->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) region.start = (first << 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) region.end = (last << 21) + ((1 << 21) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pcibios_bus_to_resource(dev->bus, res, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) apb_calc_first_last(map, &first, &last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) res = bus->resource[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) region.start = (first << 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) region.end = (last << 29) + ((1 << 29) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pcibios_bus_to_resource(dev->bus, res, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void pci_of_scan_bus(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) const u32 *busrange, *ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int len, i, simba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* parse bus-range property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) busrange = of_get_property(node, "bus-range", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (busrange == NULL || len != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pci_info(dev, " Bridge bus range [%u --> %u]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) busrange[0], busrange[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ranges = of_get_property(node, "ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) simba = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ranges == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) const char *model = of_get_property(node, "model", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (model && !strcmp(model, "SUNW,simba"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) simba = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pci_err(dev, "Failed to create pci bus for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bus->primary = dev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bus->bridge_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ranges, simba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* parse ranges property, or cook one up by hand for Simba */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* PCI #address-cells == 3 and #size-cells == 2 always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) res = &dev->resource[PCI_BRIDGE_RESOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) res->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bus->resource[i] = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ++res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (simba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) apb_fake_ranges(dev, bus, pbm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto after_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) } else if (ranges == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_read_bridge_bases(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto after_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) for (; len >= 32; len -= 32, ranges += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "%08x:%08x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ranges[0], ranges[1], ranges[2], ranges[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ranges[4], ranges[5], ranges[6], ranges[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) flags = pci_parse_of_flags(ranges[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) size = GET_64BIT(ranges, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (flags == 0 || size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* On PCI-Express systems, PCI bridges that have no devices downstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * have a bogus size value where the first 32-bit cell is 0xffffffff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * This results in a bogus range where start + size overflows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Just skip these otherwise the kernel will complain when the resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * tries to be claimed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (size >> 32 == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) res = bus->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (res->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pci_err(dev, "ignoring extra I/O range"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) " for bridge %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pci_err(dev, "too many memory ranges"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) " for bridge %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) res = bus->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) res->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) region.start = start = GET_64BIT(ranges, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) region.end = region.start + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) flags, start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pcibios_bus_to_resource(dev->bus, res, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) after_ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pci_info(dev, " bus name: %s\n", bus->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pci_of_scan_bus(pbm, node, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void pci_of_scan_bus(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const u32 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int reglen, devfn, prev_devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pci_info(bus, "scan_bus[%pOF] bus no %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) node, bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) prev_devfn = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) while ((child = of_get_next_child(node, child)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pci_info(bus, " * %pOF\n", child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) reg = of_get_property(child, "reg", ®len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (reg == NULL || reglen < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) devfn = (reg[0] >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* This is a workaround for some device trees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * which list PCI devices twice. On the V100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * for example, device number 3 is listed twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Once as "pm" and once again as "lomp".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (devfn == prev_devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) prev_devfn = devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* create a new pci_dev for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev = of_create_pci_dev(pbm, child, bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pci_info(dev, "dev header type: %x\n", dev->hdr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (pci_is_bridge(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) of_scan_pci_bridge(pbm, child, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dp = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void pci_bus_register_of_sysfs(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct pci_bus *child_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* we don't really care if we can create this file or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * not, but we need to assign the result of the call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * or the world will fall under alien invasion and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * everybody will be frozen on a spaceship ready to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * eaten on alpha centauri by some green and jelly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * humanoid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) (void) err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) list_for_each_entry(child_bus, &bus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pci_bus_register_of_sysfs(child_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void pci_claim_legacy_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct resource *p, *root, *conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) p = kzalloc(sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) p->name = "Video RAM area";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) region.start = 0xa0000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) region.end = region.start + 0x1ffffUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pcibios_bus_to_resource(dev->bus, p, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) root = pci_find_parent_resource(dev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!root) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) conflict = request_resource_conflict(root, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (conflict) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) p, conflict->name, conflict);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pci_info(dev, "VGA legacy framebuffer %pR\n", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void pci_claim_bus_resources(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct pci_bus *child_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct resource *r = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (r->parent || !r->start || !r->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pci_info(dev, "Claiming Resource %d: %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) i, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pci_claim_resource(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pci_claim_legacy_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) list_for_each_entry(child_bus, &bus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pci_claim_bus_resources(child_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) LIST_HEAD(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct device_node *node = pbm->op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) printk("PCI: Scanning PBM %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pci_add_resource_offset(&resources, &pbm->io_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pbm->io_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pci_add_resource_offset(&resources, &pbm->mem_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pbm->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (pbm->mem64_space.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pci_add_resource_offset(&resources, &pbm->mem64_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pbm->mem64_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pbm->busn.start = pbm->pci_first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pbm->busn.end = pbm->pci_last_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pbm->busn.flags = IORESOURCE_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pci_add_resource(&resources, &pbm->busn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pbm, &resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) printk(KERN_ERR "Failed to create bus for %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pci_free_resource_list(&resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pci_of_scan_bus(pbm, node, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pci_bus_register_of_sysfs(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pci_claim_bus_resources(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pci_bus_add_devices(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int pcibios_enable_device(struct pci_dev *dev, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u16 cmd, oldcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pci_read_config_word(dev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) oldcmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct resource *res = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Only set up the requested stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!(mask & (1<<i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cmd |= PCI_COMMAND_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (res->flags & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cmd |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (cmd != oldcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pci_write_config_word(dev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Platform support for /proc/bus/pci/X/Y mmap()s. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* If the user uses a host-bridge as the PCI device, he may use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * this to perform a raw mmap() of the I/O or MEM space behind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * that controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * This can be useful for execution of x86 PCI bios initialization code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * on a PCI card, like the xfree86 int10 stuff does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) enum pci_mmap_state mmap_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned long space_size, user_offset, user_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (mmap_state == pci_mmap_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) space_size = resource_size(&pbm->io_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) space_size = resource_size(&pbm->mem_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Make sure the request is in range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) user_offset = vma->vm_pgoff << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) user_size = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (user_offset >= space_size ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) (user_offset + user_size) > space_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (mmap_state == pci_mmap_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) vma->vm_pgoff = (pbm->io_space.start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) user_offset) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) vma->vm_pgoff = (pbm->mem_space.start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) user_offset) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Adjust vm_pgoff of VMA such that it is the physical page offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * corresponding to the 32-bit pci bus offset for DEV requested by the user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Basically, the user finds the base address for his device which he wishes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * to mmap. They read the 32-bit value from the config space base register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * offset parameter of mmap on /proc/bus/pci/XXX for that device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * Returns negative error code on failure, zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int __pci_mmap_make_offset(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) enum pci_mmap_state mmap_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned long user_paddr, user_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* First compute the physical address in vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * making sure the user offset is within range in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * appropriate PCI space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* If this is a mapping on a host bridge, any address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * is OK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Otherwise make sure it's in the range for one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * device's resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) user_paddr = vma->vm_pgoff << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) user_size = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct resource *rp = &pdev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) resource_size_t aligned_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Active? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!rp->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Same type? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (i == PCI_ROM_RESOURCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (mmap_state != pci_mmap_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if ((mmap_state == pci_mmap_io &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (rp->flags & IORESOURCE_IO) == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (mmap_state == pci_mmap_mem &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (rp->flags & IORESOURCE_MEM) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Align the resource end to the next page address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * because actually we need the address of the next byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * after rp->end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if ((rp->start <= user_paddr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) (user_paddr + user_size) <= aligned_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (i > PCI_ROM_RESOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * device mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) enum pci_mmap_state mmap_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Our io_remap_pfn_range takes care of this, do nothing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * for this architecture. The region in the process to map is described by vm_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * and vm_end members of VMA, the base physical address is found in vm_pgoff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * The pci device structure is provided so that architectures may make mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * decisions on a per-device or per-bus basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * Returns a negative error code on failure, zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int pci_mmap_page_range(struct pci_dev *dev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) enum pci_mmap_state mmap_state, int write_combine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = __pci_mmap_make_offset(dev, vma, mmap_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __pci_mmap_set_pgprot(dev, vma, mmap_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ret = io_remap_pfn_range(vma, vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) vma->vm_end - vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int pcibus_to_node(struct pci_bus *pbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct pci_pbm_info *pbm = pbus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return pbm->numa_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) EXPORT_SYMBOL(pcibus_to_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Return the domain number for this pci bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int pci_domain_nr(struct pci_bus *pbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct pci_pbm_info *pbm = pbus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!pbm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = pbm->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) EXPORT_SYMBOL(pci_domain_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!pbm->setup_msi_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return pbm->setup_msi_irq(&irq, pdev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) void arch_teardown_msi_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct msi_desc *entry = irq_get_msi_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (pbm->teardown_msi_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pbm->teardown_msi_irq(irq, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #endif /* !(CONFIG_PCI_MSI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* ALI sound chips generate 31-bits of DMA, a special register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * determines what bit 31 is emitted as.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) int ali_sound_dma_hack(struct device *dev, u64 device_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct iommu *iommu = dev->archdata.iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct pci_dev *ali_isa_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!dev_is_pci(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) device_mask != 0x7fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PCI_DEVICE_ID_AL_M1533,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (iommu->dma_addr_mask & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) val |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) val &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) pci_write_config_byte(ali_isa_bridge, 0x7e, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pci_dev_put(ali_isa_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) void pci_resource_to_user(const struct pci_dev *pdev, int bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) const struct resource *rp, resource_size_t *start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) resource_size_t *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * "User" addresses are shown in /sys/devices/pci.../.../resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * and /proc/bus/pci/devices and used as mmap offsets for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * On sparc, these are PCI bus addresses, i.e., raw BAR values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) *start = region.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) *end = region.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) void pcibios_set_master(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* No special bus mastering setup handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int pcibios_add_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Add sriov arch specific initialization here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * Copy dev_archdata from PF to VF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (dev->is_virtfn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct dev_archdata *psd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pdev = dev->physfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) psd = &pdev->dev.archdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) psd->stc, psd->host_controller, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) psd->numa_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #endif /* CONFIG_PCI_IOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) pci_dfl_cache_line_size = 64 >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) subsys_initcall(pcibios_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #ifdef CONFIG_SYSFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void pcie_bus_slot_names(struct pci_bus *pbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) list_for_each_entry(pdev, &pbus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) char name[SLOT_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct pci_slot *pci_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) const u32 *slot_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) slot_num = of_get_property(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "physical-slot#", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (slot_num == NULL || len != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) snprintf(name, sizeof(name), "%u", slot_num[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (IS_ERR(pci_slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) pr_err("PCI: pci_create_slot returned %ld.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PTR_ERR(pci_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) list_for_each_entry(bus, &pbus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pcie_bus_slot_names(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) const struct pci_slot_names {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u32 slot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) char names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) } *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) const char *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) prop = of_get_property(node, "slot-names", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mask = prop->slot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) sp = prop->names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) node, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct pci_slot *pci_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u32 this_bit = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!(mask & this_bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (ofpci_verbose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pci_info(bus, "Making slot [%s]\n", sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) pci_slot = pci_create_slot(bus, i, sp, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (IS_ERR(pci_slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) pci_err(bus, "pci_create_slot returned %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PTR_ERR(pci_slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) sp += strlen(sp) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) mask &= ~this_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static int __init of_pci_slot_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct pci_bus *pbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) while ((pbus = pci_find_next_bus(pbus)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pdev = list_first_entry(&pbus->devices, struct pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) bus_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (pdev && pci_is_pcie(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pcie_bus_slot_names(pbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (pbus->self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* PCI->PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) node = pbus->self->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct pci_pbm_info *pbm = pbus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Host PCI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) node = pbm->op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pci_bus_slot_names(node, pbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) device_initcall(of_pci_slot_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags