Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 	/* The registers for cross calls will be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	 * DATA 0: [low 32-bits]  Address of function to call, jmp to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	 *         [high 32-bits] MMU Context Argument 0, place in %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	 * DATA 1: Address Argument 1, place in %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	 * DATA 2: Address Argument 2, place in %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	 * With this method we can do most of the cross-call tlb/cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	 * flushing very quickly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	.align		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	.globl		do_ivec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	.type		do_ivec,#function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) do_ivec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	mov		0x40, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	ldxa		[%g3 + %g0] ASI_INTR_R, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	sethi		%hi(KERNBASE), %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	cmp		%g3, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	bgeu,pn		%xcc, do_ivec_xcall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	 srlx		%g3, 32, %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	stxa		%g0, [%g0] ASI_INTR_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	sethi		%hi(ivector_table_pa), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	ldx		[%g2 + %lo(ivector_table_pa)], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	sllx		%g3, 4, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	add		%g2, %g3, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	TRAP_LOAD_IRQ_WORK_PA(%g6, %g1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	ldx		[%g6], %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	stxa		%g5, [%g3] ASI_PHYS_USE_EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	stx		%g3, [%g6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	wr		%g0, 1 << PIL_DEVICE_IRQ, %set_softint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) do_ivec_xcall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	mov		0x50, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	ldxa		[%g1 + %g0] ASI_INTR_R, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	srl		%g3, 0, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	mov		0x60, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	ldxa		[%g7 + %g0] ASI_INTR_R, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	stxa		%g0, [%g0] ASI_INTR_RECEIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	membar		#Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	ba,pt		%xcc, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.align		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1:	jmpl		%g3, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	 nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.size		do_ivec,.-do_ivec