^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* irq.c: UltraSparc IRQ handling/init/registry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ftrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/upa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/starfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/cpudata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/auxio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/hypervisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "entry.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "cpumap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "kstack.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ino_bucket *ivector_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long ivector_table_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* On several sun4u processors, it is illegal to mix bypass and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * non-bypass accesses. Therefore we access all INO buckets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * using bypass accesses only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) : "=&r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) : "r" (bucket_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) offsetof(struct ino_bucket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __irq_chain_pa)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "i" (ASI_PHYS_USE_EC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void bucket_clear_chain_pa(unsigned long bucket_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __asm__ __volatile__("stxa %%g0, [%0] %1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) : "r" (bucket_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) offsetof(struct ino_bucket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __irq_chain_pa)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "i" (ASI_PHYS_USE_EC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static unsigned int bucket_get_irq(unsigned long bucket_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __asm__ __volatile__("lduwa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) : "=&r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) : "r" (bucket_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) offsetof(struct ino_bucket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __irq)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "i" (ASI_PHYS_USE_EC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __asm__ __volatile__("stwa %0, [%1] %2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) : "r" (irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "r" (bucket_pa +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) offsetof(struct ino_bucket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __irq)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "i" (ASI_PHYS_USE_EC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned long hvirq_major __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int __init early_hvirq_major(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int rc = kstrtoul(p, 10, &hvirq_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) early_param("hvirq", early_hvirq_major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int hv_irq_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Major version 2.0 of HV_GRP_INTR added support for the VIRQ cookie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * based interfaces, but:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 1) Several OSs, Solaris and Linux included, use them even when only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * negotiating version 1.0 (or failing to negotiate at all). So the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * hypervisor has a workaround that provides the VIRQ interfaces even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * when only verion 1.0 of the API is in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * 2) Second, and more importantly, with major version 2.0 these VIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * interfaces only were actually hooked up for LDC interrupts, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * though the Hypervisor specification clearly stated:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * The new interrupt API functions will be available to a guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * when it negotiates version 2.0 in the interrupt API group 0x2. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * a guest negotiates version 2.0, all interrupt sources will only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * support using the cookie interface, and any attempt to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * version 1.0 interrupt APIs numbered 0xa0 to 0xa6 will result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * ENOTSUPPORTED error being returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * with an emphasis on "all interrupt sources".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * To correct this, major version 3.0 was created which does actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * support VIRQs for all interrupt sources (not just LDC devices). So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * if we want to move completely over the cookie based VIRQs we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * negotiate major version 3.0 or later of HV_GRP_INTR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static bool sun4v_cookie_only_virqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (hv_irq_version >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void __init irq_init_hv(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long hv_error, major, minor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (tlb_type != hypervisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (hvirq_major)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) major = hvirq_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) major = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hv_error = sun4v_hvapi_register(HV_GRP_INTR, major, &minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!hv_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) hv_irq_version = major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hv_irq_version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pr_info("SUN4V: Using IRQ API major %d, cookie only virqs %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hv_irq_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sun4v_cookie_only_virqs() ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* This function is for the timer interrupt.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int __init arch_probe_nr_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DEFAULT_NUM_IVECS (0xfffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static unsigned int nr_ivec = DEFAULT_NUM_IVECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define NUM_IVECS (nr_ivec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static unsigned int __init size_nr_ivec(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (tlb_type == hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) switch (sun4v_chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Athena's devhandle|devino is large.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case SUN4V_CHIP_SPARC64X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) nr_ivec = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return nr_ivec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct irq_handler_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int dev_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int dev_ino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long sysino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ino_bucket bucket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long imap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline unsigned int irq_data_to_handle(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ihd->dev_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline unsigned int irq_data_to_ino(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ihd->dev_ino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline unsigned long irq_data_to_sysino(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ihd->sysino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void irq_free(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void *data = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) irq_set_handler_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) irq_free_descs(irq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) irq = __irq_alloc_descs(-1, 1, 1, numa_node_id(), NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static unsigned int cookie_exists(u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long hv_err, cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct ino_bucket *bucket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int irq = 0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hv_err = sun4v_vintr_get_cookie(devhandle, devino, &cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (hv_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_err("HV get cookie failed hv_err = %ld\n", hv_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (cookie & ((1UL << 63UL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cookie = ~cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bucket = (struct ino_bucket *) __va(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) irq = bucket->__irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static unsigned int sysino_exists(u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct ino_bucket *bucket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) bucket = &ivector_table[sysino];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) irq = bucket_get_irq(__pa(bucket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void ack_bad_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pr_crit("BAD IRQ ack %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void irq_install_pre_handler(int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void (*func)(unsigned int, void *, void *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void *arg1, void *arg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pr_warn("IRQ pre handler NOT supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * /proc/interrupts printing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int arch_show_interrupts(struct seq_file *p, int prec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) seq_printf(p, "NMI: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for_each_online_cpu(j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) seq_printf(p, " Non-maskable interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (this_is_starfire) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tid = starfire_translate(imap, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tid <<= IMAP_TID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tid &= IMAP_TID_UPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (tlb_type == cheetah || tlb_type == cheetah_plus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __asm__ ("rdpr %%ver, %0" : "=r" (ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if ((ver >> 32UL) == __JALAPENO_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) (ver >> 32UL) == __SERRANO_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tid = cpuid << IMAP_TID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tid &= IMAP_TID_JBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int a = cpuid & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int n = (cpuid >> 5) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tid = ((a << IMAP_AID_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (n << IMAP_NID_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) tid &= (IMAP_AID_SAFARI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) IMAP_NID_SAFARI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tid = cpuid << IMAP_TID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tid &= IMAP_TID_UPA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cpumask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cpumask_copy(&mask, affinity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (cpumask_equal(&mask, cpu_online_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cpuid = map_to_cpu(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cpumask_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) cpumask_and(&tmp, cpu_online_mask, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define irq_choose_cpu(irq, affinity) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) real_hard_smp_processor_id()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void sun4u_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct irq_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (likely(handler_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long cpuid, imap, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned int tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cpuid = irq_choose_cpu(data->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) irq_data_get_affinity_mask(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) imap = handler_data->imap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tid = sun4u_compute_tid(imap, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) val = upa_readq(imap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) IMAP_AID_SAFARI | IMAP_NID_SAFARI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) val |= tid | IMAP_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) upa_writeq(val, imap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) upa_writeq(ICLR_IDLE, handler_data->iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int sun4u_set_affinity(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct irq_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (likely(handler_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned long cpuid, imap, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cpuid = irq_choose_cpu(data->irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) imap = handler_data->imap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tid = sun4u_compute_tid(imap, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val = upa_readq(imap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) IMAP_AID_SAFARI | IMAP_NID_SAFARI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val |= tid | IMAP_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) upa_writeq(val, imap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) upa_writeq(ICLR_IDLE, handler_data->iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Don't do anything. The desc->status check for IRQ_DISABLED in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * handler_irq() will skip the handler call and that will leave the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * interrupt in the sent state. The next ->enable() call will hit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * ICLR register to reset the state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * This scheme is necessary, instead of clearing the Valid bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * IMAP register, to handle the case of IMAP registers being shared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * multiple INOs (and thus ICLR registers). Since we use a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * virtual IRQ for each shared IMAP instance, the generic code thinks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * there is only one user so it prematurely calls ->disable() on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * free_irq().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * We have to provide an explicit ->disable() method instead of using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * NULL to get the default. The reason is that if the generic code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * sees that, it also hooks up a default ->shutdown method which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * invokes ->mask() which we do not want. See irq_chip_set_defaults().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void sun4u_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void sun4u_irq_eoi(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct irq_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) handler_data = irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (likely(handler_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) upa_writeq(ICLR_IDLE, handler_data->iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void sun4v_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned long cpuid = irq_choose_cpu(data->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) irq_data_get_affinity_mask(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int ino = irq_data_to_sysino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = sun4v_intr_settarget(ino, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "err(%d)\n", ino, cpuid, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) printk(KERN_ERR "sun4v_intr_setstate(%x): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "err(%d)\n", ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int sun4v_set_affinity(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long cpuid = irq_choose_cpu(data->irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int ino = irq_data_to_sysino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) err = sun4v_intr_settarget(ino, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "err(%d)\n", ino, cpuid, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void sun4v_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int ino = irq_data_to_sysino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) printk(KERN_ERR "sun4v_intr_setenabled(%x): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "err(%d)\n", ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void sun4v_irq_eoi(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int ino = irq_data_to_sysino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) printk(KERN_ERR "sun4v_intr_setstate(%x): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "err(%d)\n", ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void sun4v_virq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long dev_handle = irq_data_to_handle(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long dev_ino = irq_data_to_ino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) cpuid = irq_choose_cpu(data->irq, irq_data_get_affinity_mask(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_handle, dev_ino, cpuid, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) err = sun4v_vintr_set_state(dev_handle, dev_ino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) HV_INTR_STATE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "HV_INTR_STATE_IDLE): err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_handle, dev_ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err = sun4v_vintr_set_valid(dev_handle, dev_ino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) HV_INTR_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "HV_INTR_ENABLED): err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dev_handle, dev_ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int sun4v_virt_set_affinity(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned long dev_handle = irq_data_to_handle(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned long dev_ino = irq_data_to_ino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned long cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cpuid = irq_choose_cpu(data->irq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_handle, dev_ino, cpuid, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void sun4v_virq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned long dev_handle = irq_data_to_handle(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned long dev_ino = irq_data_to_ino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) err = sun4v_vintr_set_valid(dev_handle, dev_ino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) HV_INTR_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "HV_INTR_DISABLED): err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_handle, dev_ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static void sun4v_virq_eoi(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long dev_handle = irq_data_to_handle(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned long dev_ino = irq_data_to_ino(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err = sun4v_vintr_set_state(dev_handle, dev_ino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) HV_INTR_STATE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (err != HV_EOK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "HV_INTR_STATE_IDLE): err(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_handle, dev_ino, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static struct irq_chip sun4u_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "sun4u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .irq_enable = sun4u_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .irq_disable = sun4u_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .irq_eoi = sun4u_irq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .irq_set_affinity = sun4u_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .flags = IRQCHIP_EOI_IF_HANDLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static struct irq_chip sun4v_irq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .name = "sun4v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .irq_enable = sun4v_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .irq_disable = sun4v_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .irq_eoi = sun4v_irq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .irq_set_affinity = sun4v_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .flags = IRQCHIP_EOI_IF_HANDLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static struct irq_chip sun4v_virq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "vsun4v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .irq_enable = sun4v_virq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .irq_disable = sun4v_virq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .irq_eoi = sun4v_virq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .irq_set_affinity = sun4v_virt_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .flags = IRQCHIP_EOI_IF_HANDLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct irq_handler_data *handler_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct ino_bucket *bucket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int ino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) BUG_ON(tlb_type == hypervisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) bucket = &ivector_table[ino];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) irq = bucket_get_irq(__pa(bucket));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) irq = irq_alloc(0, ino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) bucket_set_irq(__pa(bucket), irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) irq_set_chip_and_handler_name(irq, &sun4u_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) handle_fasteoi_irq, "IVEC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) handler_data = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (unlikely(handler_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (unlikely(!handler_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) irq_set_handler_data(irq, handler_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) handler_data->imap = imap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) handler_data->iclr = iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static unsigned int sun4v_build_common(u32 devhandle, unsigned int devino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void (*handler_data_init)(struct irq_handler_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 devhandle, unsigned int devino),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct irq_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct irq_handler_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) irq = irq_alloc(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (unlikely(!data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pr_err("IRQ handler data allocation failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) irq_free(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) irq_set_handler_data(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) handler_data_init(data, devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) data->imap = ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) data->iclr = ~0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static unsigned long cookie_assign(unsigned int irq, u32 devhandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct irq_handler_data *ihd = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned long hv_error, cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* handler_irq needs to find the irq. cookie is seen signed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * sun4v_dev_mondo and treated as a non ivector_table delivery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ihd->bucket.__irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cookie = ~__pa(&ihd->bucket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) hv_error = sun4v_vintr_set_cookie(devhandle, devino, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (hv_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) pr_err("HV vintr set cookie failed = %ld\n", hv_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return hv_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void cookie_handler_data(struct irq_handler_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) data->dev_handle = devhandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) data->dev_ino = devino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static unsigned int cookie_build_irq(u32 devhandle, unsigned int devino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct irq_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned long hv_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) irq = sun4v_build_common(devhandle, devino, cookie_handler_data, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) hv_error = cookie_assign(irq, devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (hv_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) irq_free(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static unsigned int sun4v_build_cookie(u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) irq = cookie_exists(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void sysino_set_bucket(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct irq_handler_data *ihd = irq_get_handler_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct ino_bucket *bucket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unsigned long sysino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) sysino = sun4v_devino_to_sysino(ihd->dev_handle, ihd->dev_ino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) BUG_ON(sysino >= nr_ivec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) bucket = &ivector_table[sysino];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bucket_set_irq(__pa(bucket), irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static void sysino_handler_data(struct irq_handler_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned long sysino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) sysino = sun4v_devino_to_sysino(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) data->sysino = sysino;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static unsigned int sysino_build_irq(u32 devhandle, unsigned int devino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct irq_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) irq = sun4v_build_common(devhandle, devino, sysino_handler_data, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) sysino_set_bucket(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int sun4v_build_sysino(u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) irq = sysino_exists(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) irq = sysino_build_irq(devhandle, devino, &sun4v_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (sun4v_cookie_only_virqs())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) irq = sun4v_build_cookie(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) irq = sun4v_build_sysino(devhandle, devino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* This is borrowed from the original function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) irq_set_status_flags(irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) void *hardirq_stack[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void *softirq_stack[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void __irq_entry handler_irq(int pil, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned long pstate, bucket_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct pt_regs *old_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) void *orig_sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) clear_softint(1 << pil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) old_regs = set_irq_regs(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) irq_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Grab an atomic snapshot of the pending IVECs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __asm__ __volatile__("rdpr %%pstate, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "wrpr %0, %3, %%pstate\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "ldx [%2], %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "stx %%g0, [%2]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "wrpr %0, 0x0, %%pstate\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) : "=&r" (pstate), "=&r" (bucket_pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) : "r" (irq_work_pa(smp_processor_id())),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "i" (PSTATE_IE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) orig_sp = set_hardirq_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) while (bucket_pa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) unsigned long next_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) next_pa = bucket_get_chain_pa(bucket_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) irq = bucket_get_irq(bucket_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) bucket_clear_chain_pa(bucket_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) bucket_pa = next_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) restore_hardirq_stack(orig_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) irq_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) set_irq_regs(old_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) void do_softirq_own_stack(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) void *orig_sp, *sp = softirq_stack[smp_processor_id()];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) sp += THREAD_SIZE - 192 - STACK_BIAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __asm__ __volatile__("mov %%sp, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "mov %1, %%sp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) : "=&r" (orig_sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) : "r" (sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) __do_softirq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) __asm__ __volatile__("mov %0, %%sp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) : : "r" (orig_sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) void fixup_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) for (irq = 0; irq < NR_IRQS; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct irq_desc *desc = irq_to_desc(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct irq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) data = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) raw_spin_lock_irqsave(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (desc->action && !irqd_is_per_cpu(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (data->chip->irq_set_affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) data->chip->irq_set_affinity(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) irq_data_get_affinity_mask(data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) raw_spin_unlock_irqrestore(&desc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) tick_ops->disable_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct sun5_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u64 count0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u64 limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u64 count1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u64 limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct sun5_timer *prom_timers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static u64 prom_limit0, prom_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static void map_prom_timers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const unsigned int *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* PROM timer node hangs out in the top level of device siblings... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dp = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dp = dp->child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) while (dp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (of_node_name_eq(dp, "counter-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dp = dp->sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Assume if node is not present, PROM uses different tick mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * which we should not care about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!dp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) prom_timers = (struct sun5_timer *) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* If PROM is really using this, it must be mapped by him. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) addr = of_get_property(dp, "address", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) prom_printf("PROM does not have timer mapped, trying to continue.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) prom_timers = (struct sun5_timer *) 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void kill_prom_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!prom_timers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Save them away for later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) prom_limit0 = prom_timers->limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) prom_limit1 = prom_timers->limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * We turn both off here just to be paranoid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) prom_timers->limit0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) prom_timers->limit1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Wheee, eat the interrupt packet too... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) " mov 0x40, %%g2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) " ldxa [%%g0] %0, %%g1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) " ldxa [%%g2] %1, %%g1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) " stxa %%g0, [%%g0] %0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) " membar #Sync\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) : "g1", "g2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) void notrace init_irqwork_curcpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int cpu = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) trap_block[cpu].irq_worklist_pa = 0UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Please be very careful with register_one_mondo() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * sun4v_register_mondo_queues().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * On SMP this gets invoked from the CPU trampoline before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * the cpu has fully taken over the trap table from OBP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * and it's kernel stack + %g6 thread register state is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * not fully cooked yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * Therefore you cannot make any OBP calls, not even prom_printf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * from these two routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void notrace register_one_mondo(unsigned long paddr, unsigned long type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) unsigned long qmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) unsigned long num_entries = (qmask + 1) / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) status = sun4v_cpu_qconf(type, paddr, num_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (status != HV_EOK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "err %lu\n", type, paddr, num_entries, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) void notrace sun4v_register_mondo_queues(int this_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct trap_per_cpu *tb = &trap_block[this_cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) tb->cpu_mondo_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) tb->dev_mondo_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) tb->resum_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) tb->nonresum_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Each queue region must be a power of 2 multiple of 64 bytes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * size. The base real address must be aligned to the size of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * region. Thus, an 8KB queue must be 8KB aligned, for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) unsigned long size = PAGE_ALIGN(qmask + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) unsigned long order = get_order(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) unsigned long p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) p = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) prom_printf("SUN4V: Error, cannot allocate queue.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) *pa_ptr = __pa(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) unsigned long page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) void *mondo, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Make sure mondo block is 64byte aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) p = kzalloc(127, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) prom_printf("SUN4V: Error, cannot allocate mondo block.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mondo = (void *)(((unsigned long)p + 63) & ~0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) tb->cpu_mondo_block_pa = __pa(mondo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) page = get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) prom_printf("SUN4V: Error, cannot allocate cpu list page.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) tb->cpu_list_pa = __pa(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Allocate mondo and error queues for all possible cpus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static void __init sun4v_init_mondo_queues(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct trap_per_cpu *tb = &trap_block[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) alloc_one_queue(&tb->nonresum_kernel_buf_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) tb->nonresum_qmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static void __init init_send_mondo_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct trap_per_cpu *tb = &trap_block[cpu];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) init_cpu_send_mondo_info(tb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct irqaction timer_irq_action = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .name = "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static void __init irq_ivector_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) unsigned long size, order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) unsigned int ivecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* If we are doing cookie only VIRQs then we do not need the ivector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * table to process interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (sun4v_cookie_only_virqs())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ivecs = size_nr_ivec();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) size = sizeof(struct ino_bucket) * ivecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) order = get_order(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ivector_table = (struct ino_bucket *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (!ivector_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) prom_printf("Fatal error, cannot allocate ivector_table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) prom_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) __flush_dcache_range((unsigned long) ivector_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ((unsigned long) ivector_table) + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ivector_table_pa = __pa(ivector_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* Only invoked on boot processor.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) irq_init_hv();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) irq_ivector_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) map_prom_timers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) kill_prom_timer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (tlb_type == hypervisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) sun4v_init_mondo_queues();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) init_send_mondo_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (tlb_type == hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Load up the boot cpu's entries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) sun4v_register_mondo_queues(hard_smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* We need to clear any IRQ's pending in the soft interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * registers, a spurious one could be left around from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * PROM timer which we just disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) clear_softint(get_softint());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Now that ivector table is initialized, it is safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * to receive IRQ vector traps. We will normally take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * one or two right now, in case some device PROM used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * to boot us wants to speak to us. We just ignore them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "or %%g1, %0, %%g1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "wrpr %%g1, 0x0, %%pstate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) : "i" (PSTATE_IE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) : "g1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) irq_to_desc(0)->action = &timer_irq_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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