^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/cpu_type.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) struct irq_bucket {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) struct irq_bucket *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) unsigned int real_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) unsigned int pil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SUN4M_HARD_INT(x) (0x000000001 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SUN4M_SOFT_INT(x) (0x000010000 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SUN4D_MAX_BOARD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Map between the irq identifier used in hw to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * irq_bucket. The map is sufficient large to hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * the sun4d hw identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* sun4m specific type definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* This maps direct to CPU specific interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sun4m_irq_percpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* This maps direct to global interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct sun4m_irq_global {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 mask_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 mask_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 interrupt_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) extern struct sun4m_irq_global __iomem *sun4m_irq_global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* The following definitions describe the individual platform features: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FEAT_L10_CLOCKEVENT (1 << 1) /* L10 timer is used as a clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FEAT_L14_ONESHOT (1 << 2) /* L14 timer clockevent can oneshot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Platform specific configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * The individual platforms assign their platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * specifics in their init functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct sparc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void (*init_timers)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int (*build_device_irq)(struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int real_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* generic clockevent features - see FEAT_* above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* clock rate used for clock event timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* one period for clock source timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int cs_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* function to obtain offsett for cs period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int (*get_cycles_offset)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) void (*clear_clock_irq)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void (*load_profile_irq)(int cpu, unsigned int limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern struct sparc_config sparc_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void irq_link(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void irq_unlink(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void handler_irq(unsigned int pil, struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long leon_get_irqmask(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* irq_32.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* sun4m_irq.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void sun4m_nmi(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* sun4d_irq.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SUN4D_IPI_IRQ 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void sun4d_ipi_interrupt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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