^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* head.S: Initial boot code for the Sparc64 port of Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/pstate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/lsu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/dcr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/dcu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/ttable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/cpudata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/pil.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/estate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/sfafsr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* This section from from _start to sparc64_boot_end should fit into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 0x0000000000404000 to 0x0000000000408000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .globl start, _start, stext, _stext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) _start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) _stext:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) stext:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ! 0x0000000000404000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) b sparc64_boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) flushw /* Flush register file. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* This stuff has to be in sync with SILO and other potential boot loaders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Fields should be kept upward compatible and whenever any change is made,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * HdrS version should be incremented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .global root_flags, ram_flags, root_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .global sparc_ramdisk_image, sparc_ramdisk_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .global sparc_ramdisk_image64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .ascii "HdrS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .word LINUX_VERSION_CODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 0x0300 : Supports being located at other than 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 0x0202 : Supports kernel params string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 0x0201 : Supports reboot_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .half 0x0301 /* HdrS version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) root_flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .half 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) root_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .half 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ram_flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .half 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sparc_ramdisk_image:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) sparc_ramdisk_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .xword reboot_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .xword bootstr_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) sparc_ramdisk_image64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .xword 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .word _end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* PROM cif handler code address is in %o4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sparc64_boot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mov %o4, %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* We need to remap the kernel. Use position independent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * code to remap us to KERNBASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * SILO can invoke us with 32-bit address masking enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * so make sure that's clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rdpr %pstate, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) andn %g1, PSTATE_AM, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) wrpr %g1, 0x0, %pstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ba,a,pt %xcc, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .globl prom_finddev_name, prom_chosen_path, prom_root_node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .globl prom_getprop_name, prom_mmu_name, prom_peer_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .globl prom_boot_mapped_pc, prom_boot_mapping_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) prom_peer_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .asciz "peer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) prom_compatible_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .asciz "compatible"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) prom_finddev_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .asciz "finddevice"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) prom_chosen_path:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .asciz "/chosen"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) prom_cpu_path:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .asciz "/cpu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) prom_getprop_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .asciz "getprop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) prom_mmu_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .asciz "mmu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) prom_callmethod_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .asciz "call-method"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) prom_translate_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .asciz "translate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) prom_map_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .asciz "map"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) prom_unmap_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .asciz "unmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) prom_set_trap_table_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .asciz "SUNW,set-trap-table"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) prom_sun4v_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .asciz "sun4v"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) prom_niagara_prefix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .asciz "SUNW,UltraSPARC-T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) prom_sparc_prefix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .asciz "SPARC-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) prom_sparc64x_prefix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .asciz "SPARC64-X"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) prom_root_compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .skip 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) prom_cpu_compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .skip 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) prom_root_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL(prom_root_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) prom_mmu_ihandle_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) prom_boot_mapped_pc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) prom_boot_mapping_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .align 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) prom_boot_mapping_phys_high:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .xword 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) prom_boot_mapping_phys_low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .xword 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) is_sun4v:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .word 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sun4v_chip_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .word SUN4V_CHIP_INVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EXPORT_SYMBOL(sun4v_chip_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rd %pc, %l0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mov (1b - prom_peer_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mov 0, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* prom_root_node = prom_peer(0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mov (1b - prom_root_node), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) stw %l4, [%l1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mov (1b - prom_getprop_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mov (1b - prom_compatible_name), %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mov (1b - prom_root_compatible), %l5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) sub %l0, %l2, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sub %l0, %l5, %l5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* prom_getproperty(prom_root_node, "compatible",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * &prom_root_compatible, 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mov 4, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mov 64, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mov (1b - prom_finddev_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mov (1b - prom_chosen_path), %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mov (1b - prom_boot_mapped_pc), %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sub %l0, %l2, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sub %l0, %l3, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) stw %l0, [%l3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sub %sp, (192 + 128), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* chosen_node = prom_finddevice("/chosen") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mov (1b - prom_getprop_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mov (1b - prom_mmu_name), %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mov (1b - prom_mmu_ihandle_cache), %l5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sub %l0, %l2, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sub %l0, %l5, %l5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mov 4, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mov 4, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mov (1b - prom_callmethod_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mov (1b - prom_translate_name), %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sub %l0, %l2, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) lduw [%l5], %l5 ! prom_mmu_ihandle_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mov 3, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mov 5, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* PAGE align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) srlx %l0, 13, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sllx %l3, 13, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mov (1b - prom_boot_mapping_mode), %l4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sub %l0, %l4, %l4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) stw %l1, [%l4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mov (1b - prom_boot_mapping_phys_high), %l4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sub %l0, %l4, %l4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) stx %l2, [%l4 + 0x0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* 4MB align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) srlx %l3, ILOG2_4MB, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sllx %l3, ILOG2_4MB, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) stx %l3, [%l4 + 0x8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Leave service as-is, "call-method" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mov 7, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mov (1b - prom_map_name), %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) sub %l0, %l3, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Leave arg2 as-is, prom_mmu_ihandle_cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mov -1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* 4MB align the kernel image size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) set (_end - KERNBASE), %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) set ((4 * 1024 * 1024) - 1), %l4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) add %l3, %l4, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) andn %l3, %l4, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) sethi %hi(KERNBASE), %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mov (1b - prom_boot_mapping_phys_low), %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sub %l0, %l3, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ldx [%l3], %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) add %sp, (192 + 128), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sethi %hi(prom_root_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) or %g1, %lo(prom_root_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sethi %hi(prom_sun4v_name), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) or %g7, %lo(prom_sun4v_name), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mov 5, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 90: ldub [%g7], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ldub [%g1], %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cmp %g2, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bne,pn %icc, 80f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) add %g7, 1, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) subcc %g3, 1, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bne,pt %xcc, 90b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) add %g1, 1, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sethi %hi(is_sun4v), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) or %g1, %lo(is_sun4v), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mov 1, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) stw %g7, [%g1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* cpu_node = prom_finddevice("/cpu") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mov (1b - prom_finddev_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mov (1b - prom_cpu_path), %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sub %l0, %l2, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) sub %sp, (192 + 128), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mov (1b - prom_getprop_name), %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mov (1b - prom_compatible_name), %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mov (1b - prom_cpu_compatible), %l5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sub %l0, %l1, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sub %l0, %l2, %l2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) sub %l0, %l5, %l5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* prom_getproperty(cpu_node, "compatible",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * &prom_cpu_compatible, 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mov 4, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mov 1, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mov 64, %l3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) call %l7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) add %sp, (2047 + 128), %o0 ! argument array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) add %sp, (192 + 128), %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sethi %hi(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) or %g1, %lo(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sethi %hi(prom_niagara_prefix), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) or %g7, %lo(prom_niagara_prefix), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mov 17, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 90: ldub [%g7], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ldub [%g1], %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) cmp %g2, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bne,pn %icc, 89f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) add %g7, 1, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) subcc %g3, 1, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) bne,pt %xcc, 90b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) add %g1, 1, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ba,pt %xcc, 91f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 89: sethi %hi(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) or %g1, %lo(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sethi %hi(prom_sparc_prefix), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) or %g7, %lo(prom_sparc_prefix), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mov 6, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 90: ldub [%g7], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ldub [%g1], %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cmp %g2, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bne,pn %icc, 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) add %g7, 1, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) subcc %g3, 1, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bne,pt %xcc, 90b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) add %g1, 1, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) sethi %hi(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) or %g1, %lo(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ldub [%g1 + 6], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cmp %g2, 'T'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) be,pt %xcc, 70f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cmp %g2, 'M'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) be,pt %xcc, 70f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cmp %g2, 'S'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) bne,pn %xcc, 49f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 70: ldub [%g1 + 7], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cmp %g2, CPU_ID_NIAGARA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mov SUN4V_CHIP_NIAGARA3, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cmp %g2, CPU_ID_NIAGARA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mov SUN4V_CHIP_NIAGARA4, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cmp %g2, CPU_ID_NIAGARA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mov SUN4V_CHIP_NIAGARA5, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cmp %g2, CPU_ID_M6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mov SUN4V_CHIP_SPARC_M6, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cmp %g2, CPU_ID_M7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mov SUN4V_CHIP_SPARC_M7, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cmp %g2, CPU_ID_M8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mov SUN4V_CHIP_SPARC_M8, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cmp %g2, CPU_ID_SONOMA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mov SUN4V_CHIP_SPARC_SN, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ba,pt %xcc, 49f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 91: sethi %hi(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) or %g1, %lo(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ldub [%g1 + 17], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cmp %g2, CPU_ID_NIAGARA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mov SUN4V_CHIP_NIAGARA1, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cmp %g2, CPU_ID_NIAGARA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) be,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mov SUN4V_CHIP_NIAGARA2, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Athena */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) sethi %hi(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) or %g1, %lo(prom_cpu_compatible), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sethi %hi(prom_sparc64x_prefix), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) or %g7, %lo(prom_sparc64x_prefix), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mov 9, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 41: ldub [%g7], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ldub [%g1], %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cmp %g2, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bne,pn %icc, 49f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) add %g7, 1, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) subcc %g3, 1, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bne,pt %xcc, 41b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) add %g1, 1, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ba,pt %xcc, 5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mov SUN4V_CHIP_SPARC64X, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 49:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mov SUN4V_CHIP_UNKNOWN, %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 5: sethi %hi(sun4v_chip_type), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) or %g2, %lo(sun4v_chip_type), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) stw %g4, [%g2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ba,pt %xcc, spitfire_boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) cheetah_plus_boot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Preserve OBP chosen DCU and DCR register settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ba,pt %xcc, cheetah_generic_boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cheetah_boot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) wr %g1, %asr18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sllx %g7, 32, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) stxa %g7, [%g0] ASI_DCU_CONTROL_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) cheetah_generic_boot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mov TSB_EXTENSION_P, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) stxa %g0, [%g3] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) stxa %g0, [%g3] ASI_IMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mov TSB_EXTENSION_S, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) stxa %g0, [%g3] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mov TSB_EXTENSION_N, %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) stxa %g0, [%g3] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) stxa %g0, [%g3] ASI_IMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ba,a,pt %xcc, jump_to_sun4u_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spitfire_boot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Typically PROM has already enabled both MMU's and both on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * caches, but we do it here anyway just to be paranoid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) stxa %g1, [%g0] ASI_LSU_CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) jump_to_sun4u_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Make sure we are in privileged mode, have address masking,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * using the ordinary globals and have enabled floating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Again, typically PROM has left %pil at 13 or similar, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) wr %g0, 0, %fprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) set sun4u_init, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) jmpl %g2 + %g0, %g0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) __REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) sun4u_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) BRANCH_IF_SUN4V(g1, sun4v_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Set ctx 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mov PRIMARY_CONTEXT, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) stxa %g0, [%g7] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mov SECONDARY_CONTEXT, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) stxa %g0, [%g7] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ba,a,pt %xcc, sun4u_continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sun4v_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Set ctx 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mov PRIMARY_CONTEXT, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) stxa %g0, [%g7] ASI_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mov SECONDARY_CONTEXT, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) stxa %g0, [%g7] ASI_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ba,a,pt %xcc, niagara_tlb_fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sun4u_continue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ba,a,pt %xcc, spitfire_tlb_fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) niagara_tlb_fixup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mov 3, %g2 /* Set TLB type to hypervisor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) sethi %hi(tlb_type), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) stw %g2, [%g1 + %lo(tlb_type)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Patch copy/clear ops. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) sethi %hi(sun4v_chip_type), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) lduw [%g1 + %lo(sun4v_chip_type)], %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) cmp %g1, SUN4V_CHIP_NIAGARA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) be,pt %xcc, niagara_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cmp %g1, SUN4V_CHIP_NIAGARA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) be,pt %xcc, niagara2_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cmp %g1, SUN4V_CHIP_NIAGARA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) be,pt %xcc, niagara2_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cmp %g1, SUN4V_CHIP_NIAGARA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) be,pt %xcc, niagara4_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cmp %g1, SUN4V_CHIP_NIAGARA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) be,pt %xcc, niagara4_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) cmp %g1, SUN4V_CHIP_SPARC_M6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) be,pt %xcc, niagara4_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) cmp %g1, SUN4V_CHIP_SPARC_M7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) be,pt %xcc, sparc_m7_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cmp %g1, SUN4V_CHIP_SPARC_M8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) be,pt %xcc, sparc_m7_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cmp %g1, SUN4V_CHIP_SPARC_SN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) be,pt %xcc, niagara4_patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) call generic_patch_copyops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) call generic_patch_bzero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) call generic_patch_pageops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ba,a,pt %xcc, 80f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) sparc_m7_patch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) call m7_patch_copyops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) call m7_patch_bzero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) call m7_patch_pageops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ba,a,pt %xcc, 80f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) niagara4_patch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) call niagara4_patch_copyops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) call niagara4_patch_bzero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) call niagara4_patch_pageops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) call niagara4_patch_fls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ba,a,pt %xcc, 80f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) niagara2_patch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) call niagara2_patch_copyops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) call niagara_patch_bzero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) call niagara_patch_pageops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ba,a,pt %xcc, 80f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) niagara_patch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) call niagara_patch_copyops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) call niagara_patch_bzero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) call niagara_patch_pageops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Patch TLB/cache ops. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) call hypervisor_patch_cachetlbops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ba,a,pt %xcc, tlb_fixup_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) cheetah_tlb_fixup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mov 2, %g2 /* Set TLB type to cheetah+. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mov 1, %g2 /* Set TLB type to cheetah. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 1: sethi %hi(tlb_type), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) stw %g2, [%g1 + %lo(tlb_type)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Patch copy/page operations to cheetah optimized versions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) call cheetah_patch_copyops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) call cheetah_patch_copy_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) call cheetah_patch_cachetlbops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ba,a,pt %xcc, tlb_fixup_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) spitfire_tlb_fixup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Set TLB type to spitfire. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mov 0, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sethi %hi(tlb_type), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) stw %g2, [%g1 + %lo(tlb_type)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) tlb_fixup_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) sethi %hi(init_thread_union), %g6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) or %g6, %lo(init_thread_union), %g6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ldx [%g6 + TI_TASK], %g4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) wr %g0, ASI_P, %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mov 1, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) sllx %g1, THREAD_SHIFT, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) add %g6, %g1, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Set per-cpu pointer initially to zero, this makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * the boot-cpu use the in-kernel-image per-cpu areas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * before setup_per_cpu_area() is invoked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clr %g5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) wrpr %g0, 0, %wstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) wrpr %g0, 0x0, %tl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Clear the bss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sethi %hi(__bss_start), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) or %o0, %lo(__bss_start), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) sethi %hi(_end), %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) or %o1, %lo(_end), %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) call __bzero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) sub %o1, %o0, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) call prom_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mov %l7, %o0 ! OpenPROM cif handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* To create a one-register-window buffer between the kernel's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * initial stack and the last stack frame we use from the firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * do the rest of the boot from a C helper function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) call start_early_boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Not reached... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* This is meant to allow the sharing of this code between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * boot processor invocation (via setup_tba() below) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * secondary processor startup (via trampoline.S). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * former does use this code, the latter does not yet due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * to some complexities. That should be fixed up at some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * There used to be enormous complexity wrt. transferring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * over from the firmware's trap table to the Linux kernel's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * For example, there was a chicken & egg problem wrt. building
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * the OBP page tables, yet needing to be on the Linux kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * trap table (to translate PAGE_OFFSET addresses) in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * We now handle OBP tlb misses differently, via linear lookups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * into the prom_trans[] array. So that specific problem no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * longer exists. Yet, unfortunately there are still some issues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * preventing trampoline.S from using this code... ho hum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .globl setup_trap_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) setup_trap_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) save %sp, -192, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Force interrupts to be disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) rdpr %pstate, %l0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) andn %l0, PSTATE_IE, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) wrpr %o1, 0x0, %pstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rdpr %pil, %l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) wrpr %g0, PIL_NORMAL_MAX, %pil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Make the firmware call to jump over to the Linux trap table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) sethi %hi(is_sun4v), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) lduw [%o0 + %lo(is_sun4v)], %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) brz,pt %o0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) stxa %g2, [%g0] ASI_SCRATCHPAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Compute physical address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) sethi %hi(KERNBASE), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) sub %g2, %g3, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) sethi %hi(kern_base), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ldx [%g3 + %lo(kern_base)], %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) add %g2, %g3, %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sethi %hi(sparc64_ttable_tl0), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) set prom_set_trap_table_name, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) stx %g2, [%sp + 2047 + 128 + 0x00]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mov 2, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) stx %g2, [%sp + 2047 + 128 + 0x08]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mov 0, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) stx %g2, [%sp + 2047 + 128 + 0x10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) stx %o0, [%sp + 2047 + 128 + 0x18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) stx %o1, [%sp + 2047 + 128 + 0x20]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sethi %hi(p1275buf), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) or %g2, %lo(p1275buf), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ldx [%g2 + 0x08], %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) call %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) add %sp, (2047 + 128), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ba,a,pt %xcc, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 1: sethi %hi(sparc64_ttable_tl0), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) set prom_set_trap_table_name, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) stx %g2, [%sp + 2047 + 128 + 0x00]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mov 1, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) stx %g2, [%sp + 2047 + 128 + 0x08]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mov 0, %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) stx %g2, [%sp + 2047 + 128 + 0x10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) stx %o0, [%sp + 2047 + 128 + 0x18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) sethi %hi(p1275buf), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) or %g2, %lo(p1275buf), %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ldx [%g2 + 0x08], %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) call %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) add %sp, (2047 + 128), %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Start using proper page size encodings in ctx register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 2: sethi %hi(sparc64_kern_pri_context), %g3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) mov PRIMARY_CONTEXT, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 661: stxa %g2, [%g1] ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .section .sun4v_1insn_patch, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .word 661b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) stxa %g2, [%g1] ASI_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) membar #Sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) BRANCH_IF_SUN4V(o2, 1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Kill PROM timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) sethi %hi(0x80000000), %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) sllx %o2, 32, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) wr %o2, 0, %tick_cmpr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ba,a,pt %xcc, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Disable STICK_INT interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) sethi %hi(0x80000000), %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) sllx %o2, 32, %o2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) wr %o2, %asr25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) wrpr %g0, %g0, %wstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) call init_irqwork_curcpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Now we can restore interrupt state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) wrpr %l0, 0, %pstate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) wrpr %l1, 0x0, %pil
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .globl setup_tba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) setup_tba:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) save %sp, -192, %sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* The boot processor is the only cpu which invokes this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * routine, the other cpus set things up via trampoline.S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * So save the OBP trap table address here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) rdpr %tba, %g7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) sethi %hi(prom_tba), %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) or %o1, %lo(prom_tba), %o1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) stx %g7, [%o1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) call setup_trap_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) sparc64_boot_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #include "etrap_64.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #include "rtrap_64.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #include "winfixup.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #include "fpu_traps.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #include "ivec.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #include "getsetcc.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #include "utrap.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #include "spiterrs.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #include "cherrs.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #include "misctrap.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #include "syscalls.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #include "helpers.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #include "sun4v_tlb_miss.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #include "sun4v_mcd.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #include "sun4v_ivec.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #include "ktlb.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #include "tsb.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * The following skip makes sure the trap table in ttable.S is aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * on a 32K boundary as required by the v9 specs for TBA register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * We align to a 32K boundary, then we have the 32K kernel TSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .skip 0x4000 + _start - 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ! 0x0000000000408000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .globl swapper_tsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) swapper_tsb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .skip (32 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .globl swapper_4m_tsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) swapper_4m_tsb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .skip (64 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ! 0x0000000000420000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Some care needs to be exercised if you try to move the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * location of the trap table relative to other things. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * one thing there are br* instructions in some of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * trap table entires which branch back to code in ktlb.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Those instructions can only handle a signed 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * displacement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * There is a binutils bug (bugzilla #4558) which causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * the relocation overflow checks for such instructions to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * not be done correctly. So bintuils will not notice the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * error and will instead write junk into the relocation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * you'll have an unbootable kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #include "ttable_64.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ! 0x0000000000428000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #include "hvcalls.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #include "systbls_64.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .align 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .globl prom_tba, tlb_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) prom_tba: .xword 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) tlb_type: .word 0 /* Must NOT end up in BSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) EXPORT_SYMBOL(tlb_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .section ".fixup",#alloc,#execinstr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ENTRY(__retl_efault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) retl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mov -EFAULT, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ENDPROC(__retl_efault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ENTRY(__retl_o1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) retl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mov %o1, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ENDPROC(__retl_o1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ENTRY(__retl_o1_asi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) wr %o5, 0x0, %asi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) retl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mov %o1, %o0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ENDPROC(__retl_o1_asi)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags