^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* cpu.c: Dinky routines to look for the kind of Sparc cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * we are on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/psr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/cpudata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "kernel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "entry.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) EXPORT_PER_CPU_SYMBOL(__cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int ncpus_probed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int fsr_storage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct cpu_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int psr_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const char *pmu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct fpu_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int fp_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NOCPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NOFPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct manufacturer_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int psr_impl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct cpu_info cpu_info[NOCPU];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct fpu_info fpu_info[NOFPU];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CPU(ver, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .psr_vers = ver, .name = _name }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CPU_PMU(ver, _name, _pmu_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .psr_vers = ver, .name = _name, .pmu_name = _pmu_name }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FPU(ver, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .fp_vers = ver, .name = _name }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct manufacturer_info __initconst manufacturer_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Sun4/100, 4/200, SLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* borned STP1012PGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CPU(4, "Fujitsu MB86904"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CPU(5, "Fujitsu TurboSparc MB86907"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SparcStation SLC, SparcStation1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FPU(3, "Weitek WTL3170/2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* SPARCstation-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FPU(4, "Lsi Logic/Meiko L64804 or compatible"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* SparcStation2, SparcServer 490 & 690 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) CPU(0, "LSI Logic Corporation - L64811"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* SparcStation2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CPU(1, "Cypress/ROSS CY7C601"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Embedded controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CPU(3, "Cypress/ROSS CY7C611"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Ross Technologies HyperSparc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CPU(0xf, "ROSS HyperSparc RT620"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FPU(0, "ROSS HyperSparc combined IU/FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FPU(1, "Lsi Logic L64814"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FPU(2, "Texas Instruments TMS390-C602A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FPU(3, "Cypress CY7C602 FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Someone please write the code to support this beast! ;) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CPU(0, "Bipolar Integrated Technology - B5010"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CPU(0, "LSI Logic Corporation - unknown-type"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PSR_IMPL_TI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* SparcClassic -- borned STP1010TAB-50*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CPU(1, "Texas Instruments, Inc. - MicroSparc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CPU(2, "Texas Instruments, Inc. - MicroSparc II"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CPU(3, "Texas Instruments, Inc. - SuperSparc 51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CPU(4, "Texas Instruments, Inc. - SuperSparc 61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CPU(5, "Texas Instruments, Inc. - unknown"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* SuperSparc 50 module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FPU(0, "SuperSparc on-chip FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* SparcClassic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FPU(4, "TI MicroSparc on chip FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CPU(0, "Matsushita - MN10501"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FPU(0, "Matsushita MN10501"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CPU(0, "Philips Corporation - unknown"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CPU(0, "Harvest VLSI Design Center, Inc. - unknown"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CPU(0, "Systems and Processes Engineering Corporation (SPEC)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CPU(0, "Fujitsu or Weitek Power-UP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CPU(1, "Fujitsu or Weitek Power-UP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CPU(2, "Fujitsu or Weitek Power-UP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CPU(3, "Fujitsu or Weitek Power-UP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FPU(3, "Fujitsu or Weitek on-chip FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PSR_IMPL_LEON, /* Aeroflex Gaisler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CPU(3, "LEON"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FPU(2, "GRFPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FPU(3, "GRFPU-Lite"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CPU_PMU(0x11, "TI UltraSparc II (BlackBird)", "ultra12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CPU_PMU(0x12, "TI UltraSparc IIi (Sabre)", "ultra12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CPU_PMU(0x13, "TI UltraSparc IIe (Hummingbird)", "ultra12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FPU(0x10, "UltraSparc I integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FPU(0x11, "UltraSparc II integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FPU(0x12, "UltraSparc IIi integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FPU(0x13, "UltraSparc IIe integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CPU_PMU(0x10, "TI UltraSparc I (SpitFire)", "ultra12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FPU(0x10, "UltraSparc I integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .cpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CPU_PMU(0x14, "TI UltraSparc III (Cheetah)", "ultra3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CPU_PMU(0x15, "TI UltraSparc III+ (Cheetah+)", "ultra3+"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CPU_PMU(0x16, "TI UltraSparc IIIi (Jalapeno)", "ultra3i"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CPU_PMU(0x18, "TI UltraSparc IV (Jaguar)", "ultra3+"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CPU_PMU(0x19, "TI UltraSparc IV+ (Panther)", "ultra4+"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CPU_PMU(0x22, "TI UltraSparc IIIi+ (Serrano)", "ultra3i"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .fpu_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FPU(0x14, "UltraSparc III integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FPU(0x15, "UltraSparc III+ integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FPU(0x16, "UltraSparc IIIi integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FPU(0x18, "UltraSparc IV integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FPU(0x19, "UltraSparc IV+ integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FPU(-1, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* In order to get the fpu type correct, you need to take the IDPROM's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * machine type value into consideration too. I will fix this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const char *sparc_cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char *sparc_fpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) const char *sparc_pmu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __init set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const struct manufacturer_info *manuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sparc_cpu_type = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sparc_fpu_type = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sparc_pmu_type = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) manuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for (i = 0; i < ARRAY_SIZE(manufacturer_info); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (psr_impl == manufacturer_info[i].psr_impl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) manuf = &manufacturer_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (manuf != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const struct cpu_info *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct fpu_info *fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cpu = &manuf->cpu_info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) while (cpu->psr_vers != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (cpu->psr_vers == psr_vers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) sparc_cpu_type = cpu->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) sparc_pmu_type = cpu->pmu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sparc_fpu_type = "No FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cpu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fpu = &manuf->fpu_info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) while (fpu->fp_vers != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (fpu->fp_vers == fpu_vers) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) sparc_fpu_type = fpu->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) fpu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (sparc_cpu_type == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) psr_impl, psr_vers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) sparc_cpu_type = "Unknown CPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (sparc_fpu_type == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) psr_impl, fpu_vers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) sparc_fpu_type = "Unknown FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (sparc_pmu_type == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) sparc_pmu_type = "Unknown PMU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #ifdef CONFIG_SPARC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int show_cpuinfo(struct seq_file *m, void *__unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "cpu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "fpu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "promlib\t\t: Version %d Revision %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "prom\t\t: %d.%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "type\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "ncpus probed\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "ncpus active\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "CPU0Bogo\t: %lu.%02lu\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "CPU0ClkTck\t: %ld\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) sparc_cpu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) sparc_fpu_type ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) romvec->pv_romvers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) prom_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) romvec->pv_printrev >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) romvec->pv_printrev & 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &cputypval[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ncpus_probed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) num_online_cpus()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) , cpu_data(0).udelay_val/(500000/HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (cpu_data(0).udelay_val/(5000/HZ)) % 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cpu_data(0).clock_tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) smp_bogo(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mmu_info(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) smp_info(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif /* CONFIG_SPARC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_SPARC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int dcache_parity_tl1_occurred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int icache_parity_tl1_occurred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int show_cpuinfo(struct seq_file *m, void *__unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "cpu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "fpu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "pmu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "prom\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "type\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "ncpus probed\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "ncpus active\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "D$ parity tl1\t: %u\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "I$ parity tl1\t: %u\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Cpu0ClkTck\t: %016lx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sparc_cpu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sparc_fpu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sparc_pmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) prom_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ((tlb_type == hypervisor) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "sun4v" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "sun4u"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ncpus_probed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) num_online_cpus(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dcache_parity_tl1_occurred,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) icache_parity_tl1_occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) , cpu_data(0).clock_tick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cpucap_info(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) smp_bogo(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mmu_info(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) smp_info(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #endif /* CONFIG_SPARC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* The pointer we are returning is arbitrary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * it just has to be non-NULL and not IS_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * in the success case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return *pos == 0 ? &c_start : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return c_start(m, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .start =c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .show = show_cpuinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef CONFIG_SPARC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int __init cpu_type_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int psr_impl, psr_vers, fpu_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int psr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) psr_impl = ((get_psr() >> PSR_IMPL_SHIFT) & PSR_IMPL_SHIFTED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) psr_vers = ((get_psr() >> PSR_VERS_SHIFT) & PSR_VERS_SHIFTED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) psr = get_psr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) put_psr(psr | PSR_EF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (psr_impl == PSR_IMPL_LEON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) fpu_vers = get_psr() & PSR_EF ? ((get_fsr() >> 17) & 0x7) : 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) fpu_vers = ((get_fsr() >> 17) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) put_psr(psr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #endif /* CONFIG_SPARC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #ifdef CONFIG_SPARC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void __init sun4v_cpu_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) switch (sun4v_chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case SUN4V_CHIP_NIAGARA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sparc_cpu_type = "UltraSparc T1 (Niagara)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sparc_fpu_type = "UltraSparc T1 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sparc_pmu_type = "niagara";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case SUN4V_CHIP_NIAGARA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sparc_cpu_type = "UltraSparc T2 (Niagara2)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) sparc_fpu_type = "UltraSparc T2 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sparc_pmu_type = "niagara2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case SUN4V_CHIP_NIAGARA3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) sparc_cpu_type = "UltraSparc T3 (Niagara3)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sparc_fpu_type = "UltraSparc T3 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sparc_pmu_type = "niagara3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case SUN4V_CHIP_NIAGARA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sparc_cpu_type = "UltraSparc T4 (Niagara4)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sparc_fpu_type = "UltraSparc T4 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) sparc_pmu_type = "niagara4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case SUN4V_CHIP_NIAGARA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sparc_cpu_type = "UltraSparc T5 (Niagara5)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) sparc_fpu_type = "UltraSparc T5 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sparc_pmu_type = "niagara5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case SUN4V_CHIP_SPARC_M6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) sparc_cpu_type = "SPARC-M6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sparc_fpu_type = "SPARC-M6 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sparc_pmu_type = "sparc-m6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case SUN4V_CHIP_SPARC_M7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sparc_cpu_type = "SPARC-M7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) sparc_fpu_type = "SPARC-M7 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) sparc_pmu_type = "sparc-m7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case SUN4V_CHIP_SPARC_M8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sparc_cpu_type = "SPARC-M8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sparc_fpu_type = "SPARC-M8 integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sparc_pmu_type = "sparc-m8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case SUN4V_CHIP_SPARC_SN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sparc_cpu_type = "SPARC-SN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) sparc_fpu_type = "SPARC-SN integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) sparc_pmu_type = "sparc-sn";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case SUN4V_CHIP_SPARC64X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) sparc_cpu_type = "SPARC64-X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sparc_fpu_type = "SPARC64-X integrated FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sparc_pmu_type = "sparc64-x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) prom_cpu_compatible);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) sparc_cpu_type = "Unknown SUN4V CPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) sparc_fpu_type = "Unknown SUN4V FPU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) sparc_pmu_type = "Unknown SUN4V PMU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int __init cpu_type_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (tlb_type == hypervisor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sun4v_cpu_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned long ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int manuf, impl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) manuf = ((ver >> 48) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) impl = ((ver >> 32) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) set_cpu_and_fpu(manuf, impl, impl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #endif /* CONFIG_SPARC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) early_initcall(cpu_type_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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