^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* chmc.c: Driver for UltraSPARC-III memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/chmctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/cpudata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/oplib.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/head.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/memctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRV_MODULE_NAME "chmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PFX DRV_MODULE_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRV_MODULE_VERSION "0.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_VERSION(DRV_MODULE_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int mc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC_TYPE_SAFARI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MC_TYPE_JBUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static dimm_printer_t us3mc_dimm_printer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CHMCTRL_NDGRPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHMCTRL_NDIMMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* OBP memory-layout property format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct chmc_obp_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned char dimm_map[144];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned char pin_map[576];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DIMM_LABEL_SZ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct chmc_obp_mem_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* One max 8-byte string label per DIMM. Usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * this matches the label on the motherboard where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * that DIMM resides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* If symmetric use map[0], else it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * asymmetric and map[1] should be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) char symmetric;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct chmc_obp_map map[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CHMCTRL_NBANKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct chmc_bank_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct chmc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int bank_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u64 raw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int uk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int um;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int lk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int lm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct chmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct chmc_obp_mem_layout layout_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int layout_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u64 timing_control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u64 timing_control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u64 timing_control3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 timing_control4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 memaddr_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct chmc_bank_info logical_banks[CHMCTRL_NBANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define JBUSMC_REGS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define JB_MC_REG1_XOR 0x0000010000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define JB_MC_REG1_ADDR_GEN_2_SHIFT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define JB_MC_REG1_ADDR_GEN_1_SHIFT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define JB_MC_REG1_INTERLEAVE 0x0000000001800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define JB_MC_REG1_INTERLEAVE_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PART_TYPE_X8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PART_TYPE_X4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INTERLEAVE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INTERLEAVE_SAME 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define INTERLEAVE_INTERNAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INTERLEAVE_BOTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ADDR_GEN_128MB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ADDR_GEN_256MB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ADDR_GEN_512MB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ADDR_GEN_1GB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define JB_NUM_DIMM_GROUPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define JB_NUM_DIMMS_PER_GROUP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define JB_NUM_DIMMS (JB_NUM_DIMM_GROUPS * JB_NUM_DIMMS_PER_GROUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct jbusmc_obp_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char dimm_map[18];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned char pin_map[144];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct jbusmc_obp_mem_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* One max 8-byte string label per DIMM. Usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * this matches the label on the motherboard where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * that DIMM resides.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) char dimm_labels[JB_NUM_DIMMS][DIMM_LABEL_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* If symmetric use map[0], else it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * asymmetric and map[1] should be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) char symmetric;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct jbusmc_obp_map map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) char _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct jbusmc_dimm_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct jbusmc *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u64 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct jbusmc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 mc_reg_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct jbusmc_obp_mem_layout layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int layout_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int num_dimm_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct jbusmc_dimm_group dimm_groups[JB_NUM_DIMM_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static DEFINE_SPINLOCK(mctrl_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static LIST_HEAD(mctrl_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void mc_list_add(struct list_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spin_lock(&mctrl_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) list_add(list, &mctrl_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spin_unlock(&mctrl_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void mc_list_del(struct list_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_lock(&mctrl_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) list_del_init(list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spin_unlock(&mctrl_list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SYNDROME_MIN -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SYNDROME_MAX 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Covert syndrome code into the way the bits are positioned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int syndrome_to_qword_code(int syndrome_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (syndrome_code < 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) syndrome_code += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else if (syndrome_code < 128 + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) syndrome_code -= (128 - 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else if (syndrome_code < (128 + 9 + 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) syndrome_code -= (128 + 9 - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) syndrome_code -= (128 + 9 + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return syndrome_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* All this magic has to do with how a cache line comes over the wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * on Safari and JBUS. A 64-bit line comes over in 1 or more quadword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * cycles, each of which transmit ECC/MTAG info as well as the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define L2_LINE_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define L2_LINE_ADDR_MSK (L2_LINE_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define QW_PER_LINE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define QW_BYTES (L2_LINE_SIZE / QW_PER_LINE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define QW_BITS 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SAFARI_LAST_BIT (576 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define JBUS_LAST_BIT (144 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void get_pin_and_dimm_str(int syndrome_code, unsigned long paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int *pin_p, char **dimm_str_p, void *_prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int base_dimm_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int qword_code = syndrome_to_qword_code(syndrome_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int cache_line_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int offset_inverse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int dimm_map_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int map_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (mc_type == MC_TYPE_JBUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct jbusmc_obp_mem_layout *p = _prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* JBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cache_line_offset = qword_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) offset_inverse = (JBUS_LAST_BIT - cache_line_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dimm_map_index = offset_inverse / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) map_val = p->map.dimm_map[dimm_map_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) map_val = ((map_val >> ((7 - (offset_inverse & 7)))) & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *pin_p = p->map.pin_map[cache_line_offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct chmc_obp_mem_layout *p = _prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct chmc_obp_map *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int qword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Safari */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (p->symmetric)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mp = &p->map[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mp = &p->map[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) qword = (paddr & L2_LINE_ADDR_MSK) / QW_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cache_line_offset = ((3 - qword) * QW_BITS) + qword_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) offset_inverse = (SAFARI_LAST_BIT - cache_line_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dimm_map_index = offset_inverse >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) map_val = mp->dimm_map[dimm_map_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) map_val = ((map_val >> ((3 - (offset_inverse & 3)) << 1)) & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *dimm_str_p = p->dimm_labels[base_dimm_offset + map_val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *pin_p = mp->pin_map[cache_line_offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct jbusmc_dimm_group *jbusmc_find_dimm_group(unsigned long phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct jbusmc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) list_for_each_entry(p, &mctrl_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (i = 0; i < p->num_dimm_groups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct jbusmc_dimm_group *dp = &p->dimm_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (phys_addr < dp->base_addr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) (dp->base_addr + dp->size) <= phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int jbusmc_print_dimm(int syndrome_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) char *buf, int buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct jbusmc_obp_mem_layout *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct jbusmc_dimm_group *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct jbusmc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int first_dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dp = jbusmc_find_dimm_group(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (dp == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) syndrome_code < SYNDROME_MIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) syndrome_code > SYNDROME_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) buf[0] = '?';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) buf[1] = '?';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) buf[2] = '?';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) buf[3] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) p = dp->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) prop = &p->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) first_dimm = dp->index * JB_NUM_DIMMS_PER_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (syndrome_code != SYNDROME_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) char *dimm_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) &dimm_str, prop, first_dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sprintf(buf, "%s, pin %3d", dimm_str, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Multi-bit error, we just dump out all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * dimm labels associated with this dimm group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) for (dimm = 0; dimm < JB_NUM_DIMMS_PER_GROUP; dimm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) sprintf(buf, "%s ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) prop->dimm_labels[first_dimm + dimm]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) buf += strlen(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static u64 jbusmc_dimm_group_size(u64 base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) const struct linux_prom64_registers *mem_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int num_mem_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u64 max = base + (8UL * 1024 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u64 max_seen = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < num_mem_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct linux_prom64_registers *ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u64 this_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u64 this_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ent = &mem_regs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) this_base = ent->phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) this_end = this_base + ent->reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (base < this_base || base >= this_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (this_end > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) this_end = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (this_end > max_seen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) max_seen = this_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return max_seen - base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void jbusmc_construct_one_dimm_group(struct jbusmc *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct linux_prom64_registers *mem_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int num_mem_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct jbusmc_dimm_group *dp = &p->dimm_groups[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dp->controller = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dp->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dp->base_addr = (p->portid * (64UL * 1024 * 1024 * 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dp->base_addr += (index * (8UL * 1024 * 1024 * 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dp->size = jbusmc_dimm_group_size(dp->base_addr, mem_regs, num_mem_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void jbusmc_construct_dimm_groups(struct jbusmc *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const struct linux_prom64_registers *mem_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int num_mem_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (p->mc_reg_1 & JB_MC_REG1_DIMM1_BANK0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) jbusmc_construct_one_dimm_group(p, 0, mem_regs, num_mem_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) p->num_dimm_groups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (p->mc_reg_1 & JB_MC_REG1_DIMM2_BANK2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) jbusmc_construct_one_dimm_group(p, 1, mem_regs, num_mem_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) p->num_dimm_groups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int jbusmc_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct linux_prom64_registers *mem_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct device_node *mem_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int err, len, num_mem_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct jbusmc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const u32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) const void *ml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mem_node = of_find_node_by_path("/memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!mem_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) printk(KERN_ERR PFX "Cannot find /memory node.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mem_regs = of_get_property(mem_node, "reg", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!mem_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) printk(KERN_ERR PFX "Cannot get reg property of /memory node.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) num_mem_regs = len / sizeof(*mem_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) p = kzalloc(sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) printk(KERN_ERR PFX "Cannot allocate struct jbusmc.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) INIT_LIST_HEAD(&p->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) prop = of_get_property(op->dev.of_node, "portid", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!prop || len != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) printk(KERN_ERR PFX "Cannot find portid.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) p->portid = *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) prop = of_get_property(op->dev.of_node, "memory-control-register-1", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!prop || len != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) printk(KERN_ERR PFX "Cannot get memory control register 1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) p->mc_reg_1 = ((u64)prop[0] << 32) | (u64) prop[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) p->regs = of_ioremap(&op->resource[0], 0, JBUSMC_REGS_SIZE, "jbusmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!p->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) printk(KERN_ERR PFX "Cannot map jbusmc regs.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ml = of_get_property(op->dev.of_node, "memory-layout", &p->layout_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!ml) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) printk(KERN_ERR PFX "Cannot get memory layout property.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (p->layout_len > sizeof(p->layout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) printk(KERN_ERR PFX "Unexpected memory-layout size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) p->layout_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) memcpy(&p->layout, ml, p->layout_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) jbusmc_construct_dimm_groups(p, mem_regs, num_mem_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mc_list_add(&p->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) printk(KERN_INFO PFX "UltraSPARC-IIIi memory controller at %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_set_drvdata(&op->dev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Does BANK decode PHYS_ADDR? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Bank must be enabled to match. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (bp->valid == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Would BANK match upper bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) upper_bits ^= bp->um; /* What bits are different? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) upper_bits = ~upper_bits; /* Invert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) upper_bits |= bp->uk; /* What bits don't matter for matching? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) upper_bits = ~upper_bits; /* Invert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (upper_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Would BANK match lower bits? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) lower_bits ^= bp->lm; /* What bits are different? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) lower_bits = ~lower_bits; /* Invert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) lower_bits |= bp->lk; /* What bits don't matter for matching? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) lower_bits = ~lower_bits; /* Invert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (lower_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* I always knew you'd be the one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Given PHYS_ADDR, search memory controller banks for a match. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct chmc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) list_for_each_entry(p, &mctrl_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int bank_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct chmc_bank_info *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bp = &p->logical_banks[bank_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (chmc_bank_match(bp, phys_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* This is the main purpose of this driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int chmc_print_dimm(int syndrome_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned long phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) char *buf, int buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct chmc_bank_info *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct chmc_obp_mem_layout *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int bank_in_controller, first_dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bp = chmc_find_bank(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (bp == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) syndrome_code < SYNDROME_MIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) syndrome_code > SYNDROME_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) buf[0] = '?';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) buf[1] = '?';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) buf[2] = '?';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) buf[3] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) prop = &bp->p->layout_prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) first_dimm *= CHMCTRL_NDIMMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (syndrome_code != SYNDROME_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) char *dimm_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) get_pin_and_dimm_str(syndrome_code, phys_addr, &pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) &dimm_str, prop, first_dimm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sprintf(buf, "%s, pin %3d", dimm_str, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Multi-bit error, we just dump out all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * dimm labels associated with this bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sprintf(buf, "%s ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) prop->dimm_labels[first_dimm + dimm]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) buf += strlen(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Accessing the registers is slightly complicated. If you want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * to get at the memory controller which is on the same processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * the code is executing, you must use special ASI load/store else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * you go through the global mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned long ret, this_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) this_cpu = real_hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (p->portid == this_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) : "=r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) : "r" (offset), "i" (ASI_MCU_CTRL_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) : "=r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) : "r" (p->regs + offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #if 0 /* currently unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (p->portid == smp_processor_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __asm__ __volatile__("stxa %0, [%1] %2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) : : "r" (val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "r" (offset), "i" (ASI_MCU_CTRL_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __asm__ __volatile__("ldxa %0, [%1] %2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) : : "r" (val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "r" (p->regs + offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct chmc_bank_info *bp = &p->logical_banks[which_bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) bp->p = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bp->raw_reg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bp->base = (bp->um);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) bp->base &= ~(bp->uk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bp->base <<= PA_UPPER_BITS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) switch(bp->lk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case 0xf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bp->interleave = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case 0xe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) bp->interleave = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case 0xc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) bp->interleave = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case 0x8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bp->interleave = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case 0x0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) bp->interleave = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* UK[10] is reserved, and UK[11] is not set for the SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * bank size definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) bp->size = (((unsigned long)bp->uk &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) bp->size /= bp->interleave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void chmc_fetch_decode_regs(struct chmc *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (p->layout_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) chmc_interpret_one_decode_reg(p, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) chmc_read_mcreg(p, CHMCTRL_DECODE1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) chmc_interpret_one_decode_reg(p, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) chmc_read_mcreg(p, CHMCTRL_DECODE2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) chmc_interpret_one_decode_reg(p, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) chmc_read_mcreg(p, CHMCTRL_DECODE3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) chmc_interpret_one_decode_reg(p, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) chmc_read_mcreg(p, CHMCTRL_DECODE4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int chmc_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct device_node *dp = op->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned long ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const void *pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int len, portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct chmc *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) __asm__ ("rdpr %%ver, %0" : "=r" (ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if ((ver >> 32UL) == __JALAPENO_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) (ver >> 32UL) == __SERRANO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) portid = of_getintprop_default(dp, "portid", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (portid == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) pval = of_get_property(dp, "memory-layout", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (pval && len > sizeof(p->layout_prop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) printk(KERN_ERR PFX "Unexpected memory-layout property "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "size %d.\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) p = kzalloc(sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) p->portid = portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) p->layout_size = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!pval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) p->layout_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) memcpy(&p->layout_prop, pval, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!p->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) printk(KERN_ERR PFX "Could not map registers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (p->layout_size != 0UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) chmc_fetch_decode_regs(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mc_list_add(&p->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) printk(KERN_INFO PFX "UltraSPARC-III memory controller at %pOF [%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) (p->layout_size ? "ACTIVE" : "INACTIVE"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_set_drvdata(&op->dev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int us3mc_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (mc_type == MC_TYPE_SAFARI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return chmc_probe(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) else if (mc_type == MC_TYPE_JBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return jbusmc_probe(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void chmc_destroy(struct platform_device *op, struct chmc *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) list_del(&p->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) of_iounmap(&op->resource[0], p->regs, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void jbusmc_destroy(struct platform_device *op, struct jbusmc *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mc_list_del(&p->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) of_iounmap(&op->resource[0], p->regs, JBUSMC_REGS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) kfree(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int us3mc_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) void *p = dev_get_drvdata(&op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (mc_type == MC_TYPE_SAFARI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) chmc_destroy(op, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) else if (mc_type == MC_TYPE_JBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) jbusmc_destroy(op, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct of_device_id us3mc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .name = "memory-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) MODULE_DEVICE_TABLE(of, us3mc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct platform_driver us3mc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .name = "us3mc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .of_match_table = us3mc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .probe = us3mc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .remove = us3mc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static inline bool us3mc_platform(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (tlb_type == cheetah || tlb_type == cheetah_plus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int __init us3mc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned long ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!us3mc_platform())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if ((ver >> 32UL) == __JALAPENO_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (ver >> 32UL) == __SERRANO_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mc_type = MC_TYPE_JBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) us3mc_dimm_printer = jbusmc_print_dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mc_type = MC_TYPE_SAFARI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) us3mc_dimm_printer = chmc_print_dimm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = register_dimm_printer(us3mc_dimm_printer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = platform_driver_register(&us3mc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unregister_dimm_printer(us3mc_dimm_printer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static void __exit us3mc_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (us3mc_platform()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unregister_dimm_printer(us3mc_dimm_printer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) platform_driver_unregister(&us3mc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) module_init(us3mc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) module_exit(us3mc_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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