^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * winmacro.h: Window loading-unloading macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_WINMACRO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_WINMACRO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Store the register window onto the 8-byte aligned area starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * at %reg. It might be %sp, it might not, we don't care.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STORE_WINDOW(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) std %l0, [%reg + RW_L0]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) std %l2, [%reg + RW_L2]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) std %l4, [%reg + RW_L4]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) std %l6, [%reg + RW_L6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) std %i0, [%reg + RW_I0]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) std %i2, [%reg + RW_I2]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) std %i4, [%reg + RW_I4]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) std %i6, [%reg + RW_I6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Load a register window from the area beginning at %reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LOAD_WINDOW(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ldd [%reg + RW_L0], %l0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ldd [%reg + RW_L2], %l2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ldd [%reg + RW_L4], %l4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ldd [%reg + RW_L6], %l6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ldd [%reg + RW_I0], %i0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ldd [%reg + RW_I2], %i2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ldd [%reg + RW_I4], %i4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ldd [%reg + RW_I6], %i6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Loading and storing struct pt_reg trap frames. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LOAD_PT_INS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LOAD_PT_GLOBALS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LOAD_PT_YREG(base_reg, scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ld [%base_reg + STACKFRAME_SZ + PT_Y], %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) wr %scratch, 0x0, %y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ld [%base_reg + STACKFRAME_SZ + PT_PSR], %pt_psr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ld [%base_reg + STACKFRAME_SZ + PT_PC], %pt_pc; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ld [%base_reg + STACKFRAME_SZ + PT_NPC], %pt_npc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LOAD_PT_ALL(base_reg, pt_psr, pt_pc, pt_npc, scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) LOAD_PT_YREG(base_reg, scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) LOAD_PT_INS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) LOAD_PT_GLOBALS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) LOAD_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STORE_PT_INS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) std %i2, [%base_reg + STACKFRAME_SZ + PT_I2]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) std %i4, [%base_reg + STACKFRAME_SZ + PT_I4]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) std %i6, [%base_reg + STACKFRAME_SZ + PT_I6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STORE_PT_GLOBALS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) std %g2, [%base_reg + STACKFRAME_SZ + PT_G2]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) std %g6, [%base_reg + STACKFRAME_SZ + PT_G6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STORE_PT_YREG(base_reg, scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rd %y, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) st %scratch, [%base_reg + STACKFRAME_SZ + PT_Y];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STORE_PT_PRIV(base_reg, pt_psr, pt_pc, pt_npc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) st %pt_psr, [%base_reg + STACKFRAME_SZ + PT_PSR]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) st %pt_pc, [%base_reg + STACKFRAME_SZ + PT_PC]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) st %pt_npc, [%base_reg + STACKFRAME_SZ + PT_NPC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STORE_PT_ALL(base_reg, reg_psr, reg_pc, reg_npc, g_scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) STORE_PT_PRIV(base_reg, reg_psr, reg_pc, reg_npc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) STORE_PT_GLOBALS(base_reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) STORE_PT_YREG(base_reg, g_scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) STORE_PT_INS(base_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SAVE_BOLIXED_USER_STACK(cur_reg, scratch) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ld [%cur_reg + TI_W_SAVED], %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sll %scratch, 2, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) add %scratch, %cur_reg, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) st %sp, [%scratch + TI_RWIN_SPTRS]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sub %scratch, %cur_reg, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) sll %scratch, 4, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) add %scratch, %cur_reg, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) STORE_WINDOW(scratch + TI_REG_WINDOW); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) sub %scratch, %cur_reg, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) srl %scratch, 6, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) add %scratch, 1, %scratch; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) st %scratch, [%cur_reg + TI_W_SAVED];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LOAD_CURRENT(dest_reg, idreg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 661: rd %tbr, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) srl %idreg, 10, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) and %idreg, 0xc, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .section .cpuid_patch, "ax"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Instruction location. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .word 661b; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* SUN4D implementation. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) lda [%g0] ASI_M_VIKING_TMP1, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) sll %idreg, 2, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) nop; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* LEON implementation. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rd %asr17, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) srl %idreg, 0x1c, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) sll %idreg, 0x02, %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .previous; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sethi %hi(current_set), %dest_reg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) or %dest_reg, %lo(current_set), %dest_reg;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ld [%idreg + %dest_reg], %dest_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LOAD_CURRENT(dest_reg, idreg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sethi %hi(current_set), %idreg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ld [%idreg + %lo(current_set)], %dest_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif /* !(_SPARC_WINMACRO_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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