Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _SPARC64_VISASM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _SPARC64_VISASM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* visasm.h:  FPU saving macros for VIS routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/pstate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define VISEntry					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	rd		%fprs, %o5;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	andcc		%o5, (FPRS_FEF|FPRS_DU), %g0;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	be,pt		%icc, 297f;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	 sethi		%hi(297f), %g7;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	sethi		%hi(VISenter), %g1;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	jmpl		%g1 + %lo(VISenter), %g0;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	 or		%g7, %lo(297f), %g7;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 297:	wr		%g0, FPRS_FEF, %fprs;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VISExit						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	wr		%g0, 0, %fprs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * Must preserve %o5 between VISEntryHalf and VISExitHalf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VISEntryHalf					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	VISEntry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VISExitHalf					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	VISExit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VISEntryHalfFast(fail_label)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	rd		%fprs, %o5;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	andcc		%o5, FPRS_FEF, %g0;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	be,pt		%icc, 297f;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	 nop;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	ba,a,pt		%xcc, fail_label;		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 297:	wr		%o5, FPRS_FEF, %fprs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VISExitHalfFast					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	wr		%o5, 0, %fprs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline void save_and_clear_fpu(void) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "		rd %%fprs, %%o5\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "		andcc %%o5, %0, %%g0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "		be,pt %%icc, 299f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "		 sethi %%hi(298f), %%g7\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "		sethi %%hi(VISenter), %%g1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "		jmpl %%g1 + %%lo(VISenter), %%g0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "		 or %%g7, %%lo(298f), %%g7\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "	298:	wr %%g0, 0, %%fprs\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "	299:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "		" : : "i" (FPRS_FEF|FPRS_DU) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		"o5", "g1", "g2", "g3", "g7", "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int vis_emul(struct pt_regs *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* _SPARC64_ASI_H */